Realtek Ameba-D RTL872 D Series User Manual page 256

a) Reads that indicate IC_RAW_INTR_STAT[5] (R_RD_REQ bit field) being set to 1 must be treated as the equivalent of the RD_REQ
interrupt being asserted.
b) Software must then act to satisfy the I
(4) If there is any data remaining in the Tx FIFO before receiving the read request, then the I
IC_RAW_INTR_STAT register) to flush the old data from the Tx FIFO.
Note: Because the I 2 C's Tx FIFO is forced into a flushed/reset state whenever a TX_ABRT Interrupt clear event occurs, it is necessary for
software to release the I
register IC_RAW_INTR_STAT for more details.
a) Reads that indicate bit 6 (R_TX_ABRT) being set to 1 must be treated as the equivalent of the TX_ABRT interrupt being asserted.
b) There is no further action required from software.
(5) Software writes to the IC_DATA_CMD register with the data to be written (by writing a '0' in bit 8).
(6) Software must clear the RD_REQ and TX_ABRT interrupts (bits 5 and 6, respectively) of the IC_RAW_INTR_STAT register before
proceeding.
(7) The I 2 C releases the SCL and transmits the byte.
(8) The master may hold the I
13.2.8.1.3 Slave-Receiver Operation for A Single Byte
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When another I C master device on the bus addresses the I
(1) The other I 2 C master device initiates an I
(2) The I 2 C acknowledges the sent address and recognizes the direction of the transfer to indicate that the I
(3) I 2 C receives the transmitted byte and places it in the receive buffer.
Note: If the Rx FIFO is completely filled with data when a byte is pushed, then an overflow occurs and the I
I 2 C transfers. Because a NACK is not generated, software must recognize the overflow when indicated by the I
the IC_INTR_STAT register) and take appropriate actions to recover from lost data. Hence, there is a real time constraint on software to
service the Rx FIFO before the latter overflow as there is no way to reapply pressure to the remote transmitting master. You must select a
deep enough Rx FIFO depth to satisfy the interrupt service interval of their system.
(4) I 2 C asserts the RX_FULL interrupt (IC_RAW_INTR_STAT[2] register).
If the RX_FULL interrupt has been masked, due to setting IC_INTR_MASK[2] register to 0 or setting IC_TX_TL to a value larger than 0, then
it is recommended that a timing routine be implemented for periodic reads of the IC_STATUS register. Reads of the IC_STATUS register,
with bit 3 (RFNE) set at 1, must then be treated by software as the equivalent of the RX_FULL interrupt being asserted.
(5) Software may read the byte from the IC_DATA_CMD register (bits 7:0).
(6) The other master device may hold the I
13.2.8.1.4 Slave-Transfer Operation for Bulk Transfers
In the standard I 2 C protocol, all transactions are single byte transactions and the programmer responds to a remote master read request by
writing one byte into the slave's Tx FIFO. When a slave (slave-transmitter) is issued with a read request (RD_REQ) from the remote master
(master-receiver), at a minimum there should be at least one entry placed into the slave-transmitter's Tx FIFO. I
data in the Tx FIFO so that subsequent read requests can take that data without raising an interrupt to get more data. Ultimately, this
eliminates the possibility of significant latencies being incurred between raising the interrupt for data each time had there been a restriction of
having only one entry placed in the Tx FIFO.
2
This mode only occurs when I
there is no data in the slave's Tx FIFO, the I
be written into the Tx FIFO before it can be sent to the remote master.
If the RD_REQ interrupt is masked, due to bit 5 (M_RD_REQ) of the IC_INTR_STAT register being set to 0, then it is recommended that a timing
routine be used to activate periodic reads of the IC_RAW_INTR_STAT register. Reads of IC_RAW_INTR_STAT that return bit 5 (R_RD_REQ) set
to 1 must be treated as the equivalent of the RD_REQ interrupt referred to in this section.
The RD_REQ interrupt is raised upon a read request, and like interrupts, must be cleared when exiting the interrupt service handling routine
(ISR). The ISR allows you to either write 1 byte or more than 1 byte into the Tx FIFO. During the transmission of these bytes to the master, if the
master acknowledges the last byte, then the slave must raise the RD_REQ again because the master is requesting for more data.
If the programmer knows in advance that the remote master is requesting a packet of n bytes, then when another master addresses I
requests data, the Tx FIFO could be written with n number bytes and the remote master receives it as a continuous stream of data. For
User Manual
2
C transfer.
2 C from this state by reading the IC_CLR_TX_ABRT register before attempting to write into the Tx FIFO. See
2 C bus by issuing a RESTART condition or release the bus by issuing a STOP condition.
2
2 C transfer with an address that matches the I
2
C bus by issuing a RESTART condition or release the bus by issuing a STOP condition.
C is acting as a slave-transmitter. If the remote master acknowledges the data sent by the slave-transmitter and
2 C holds the I 2 C SCL line low while it raises the read request interrupt (RD_REQ) and waits for data to
All information provided in this document is subject to legal disclaimers.
2
C and is sending data, the I C acts as a slave-receiver and the following steps occur:
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Ameba-D User Manual
2
C asserts a TX_ABRT interrupt (bit 6 of the
2 C's slave address in the IC_SAR register.
2 C is acting as a slave-receiver.
2 C continues with subsequent
2 C (by the R_RX_OVER bit in
2 C is designed to handle more
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2
C and