Realtek Ameba-D RTL872 D Series User Manual page 394

18.4.2.2 SI_CLK_EN

Name: Audio codec clock control register

Size: 32 bits

Address offset: 0x0004

Read/write access: read/write
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Bit Field Access
31:1 RSVD N/A
0 REG_CLK_EN R/W
User Manual
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RSVD
Reset Description
0 Reserved

1 1'b1: Turn on the clock of the register bank of audio codec.

1'b0: Turn off the clock.
To save power, reset this bit to gate clock when the registers are already programmed.
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Ameba-D User Manual
3 2 1 0
REG_CLK_EN
R/W
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