Realtek Ameba-D RTL872 D Series User Manual page 200

Ameba-D User Manual
The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The contents of the
preload register are transferred into the shadow register permanently or at each update event depending on the ARPE bit in the TIMx_CR
register. The update event is sent when the counter reaches the overflow and if the UDIS bit equals to 0 in the TIMx_CR register. It can also be
generated by software.
The prescaler can divide the counter clock frequency by any factor between 1 and 256. It is based on a 8-bit counter controlled through a 8-bit
register (in the TIMx_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account
at the next update event.
Fig 10-6 and Fig 10-7 give some examples of the counter behavior when the prescaler ratio is changed on the fly.
CK_PSC
CEN
Timer clock=CK_CNT
F8 F9 FA FB FC 00 01
F7 02 03
Counter register
Update event (UEV)
0 1
Prescaler control register
Write a new value in TIMx_PSC
Prescaler buffer
0
1
Prescaler counter
0 1 1 1 0
F7 0 1 0 0
Fig 10-6 Counter timing diagram with prescaler division change from 1 to 2
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