Realtek Ameba-D RTL872 D Series User Manual page 267

13.3.2.10 IC_HS_SCL_HCNT

Name: High Speed I 2 C Clock SCL High Count Register

Size: 32 bits

Address offset: 0x24

Read/write access: read/write
31 30 29
Bit Name
31:16 RSVD
15:0 IC_HS_SCL_HCNT
13.3.2.11 IC_HS_SCL_LCNT

2
Name: High Speed I C Clock SCL Low Count Register

Size: 32 bits

Address offset: 0x28

Read/write access: read/write
31 30 29
Bit Name
31:16 RSVD
15:0 IC_HS_SCL_LCNT
13.3.2.12 IC_INTR_STAT

Name: I 2 C Interrupt Status Register

Size: 32 bits

Address offset: 0x2C

Read/write access: read-only
Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt
clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register.
31 30
23 22
15 14
R_DMA_I2C_DONE R_MS_CODE_DET
User Manual
... 18 17
RSVD
Access Reset Description
N/A - Reserved
R/W 0x6 This register must be set before any I
I/O timing. This register sets the SCL clock high-period count for high speed.
The SCL High time depends on the loading of the bus. For 100pF loading, the SCL High time
is 60ns; for 400pF loading, the SCL High time is 120ns.
This register can be written only when the I
the IC_ENABLE register being set to 0. Writes at other times have no effect.
... 18 17
RSVD
Access Reset Description
N/A - Reserved
R/W 0x10 This register must be set before any I
I/O timing. This register sets the SCL clock low-period count for high speed.
The SCL low time depends on the loading of the bus. For 100pF loading, the SCL low time is
160ns; for 400pF loading, the SCL low time is 320ns.
This register can be written only when the I
the IC_ENABLE register being set to 0. Writes at other times have no effect.
29
21
13
RSVD R_ADDR_MATCH
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16 15 14
2 C bus transaction can take place to ensure proper
16 15 14
2
C bus transaction can take place to ensure proper
28 27
RSVD
20 19
RSVD
12 11
R_GEN_CALL
267
Inter-integrated Circuit (I2C) Interface
13 ... 2
IC_HS_SCL_HCNT
R/W
2
C interface is disabled, which corresponds to
13 ... 2
IC_HS_SCL_LCNT
R/W
2 C interface is disabled, which corresponds to
26 25
18 17
10 9
R_START_DET R_STOP_DET
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1 0
1 0
24
16
8
R_ACTIVITY