Realtek Ameba-D RTL872 D Series User Manual page 309

23:21 IR_RX_FILTER_STAGETX
20 RSVD
19 IR_RX_FIFO_ERROR_INT_MASK
18 IR_RX_CNT_THR_INT_MASK
17 IR_RX_FIFO_OF_INT_MASK
16 IR_RX_CNT_OF_INT_MASK
15 IR_RX_FIFO_LEVEL_INT_MASK
14 IR_RX_FIFO_FULL_INT_MASK
13 IR_RX_FIFO_DISCARD_SET
12:8 IR_RX_FIFO_LEVEL_TH
7:6 RSVD
5 IR_RX_FIFO_ERROR_INT_EN
4 IR_RX_CNT_THR_INT_EN
3 IR_RX_FIFO_OF_INT_EN
2 IR_RX_CNT_OF_INT_EN
1 IR_RX_FIFO_LEVEL_INT_EN
0 IR_RX_FIFO_FULL_INT_EN
15.3.3.2 IR_RX_SR

Name: IR clock division register
User Manual

R/W 0x0 0x0: Filter <= 20ns glitch

0x1: Filter <= 30ns glitch

0x2: Filter <= 40ns glitch

0x3: Filter <= 50ns glitch

...
N/A 0 Reserved
R/W 0x0 Rx FIFO error read interrupt
When Rx FIFO is empty, read Rx FIFO and trigger interrupt.

0: Unmask

1: Mask
R/W 0x0 Rx count threshold interrupt

0: Unmask

1: Mask
R/W 0x0 Rx FIFO overflow

0: Unmask

1: Mask
R/W 0x0 RX counter overflow

0: Unmask

1: Mask
R/W 0x0 Rx FIFO level interrupt

0: Unmask

1: Mask
When Rx FIFO offset ≥ threshold value, this interrupt is triggered.
R/W 0x0 Rx FIFO full interrupt

0: Unmask

1: Mask
R/W 0x0 When FIFO is full, new data is send to FIFO:

0: Discard oldest data in FIFO.

1: Reject new data sending to FIFO.
R/W 0x0 Rx FIFO interrupt threshold
When Rx FIFO depth > threshold value, this interrupt is triggered.
N/A 0 Reserved
R/W 0x0 Rx FIFO error read interrupt
When Rx FIFO is empty, reading the Rx FIFO triggers this interrupt.

0: Disable

1: Enable
R/W 0x0 Rx count threshold interrupt

0: Disable

1: Enable
R/W 0x0 RX FIFO overflow

0: Disable

1: Enable
R/W 0x0 RX counter overflow

0: Disable

1: Enable
R/W 0x0 Rx FIFO level interrupt
When Rx FIFO offset ≥ threshold value, this interrupt is triggered.

0: Disable

1: Enable
R/W 0x0 Rx FIFO full interrupt

0: Disable

1: Enable
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309
Infrared Radiation (IR)
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