Realtek Ameba-D RTL872 D Series User Manual page 390

21:20 SP_SEL_I2S_TX_CH
19:18 SP_ADC_COMP
17 SP_START_TX
16 SP_TX_DISABLE
15 SP_I2S_SELF_LPBK_EN
14 SP_INV_I2S_SCLK
13:12 SP_DATA_LEN_SEL
11 SP_EN_I2S_MONO
10 SP_EN_PCM_N_MODE
9:8 SP_DATA_FORMAT_SEL
7 DSP_CTL_MODE
6 SP_LOOPBACK
5 SP_WCLK_INVERSE
4 SLAVE_DATA_SEL
3 SLAVE_CLK_SEL
2 RX_INV_I2S_SCLK
1 TX_INV_I2S_SCLK
0 SP_RESET
18.4.1.3 SP_CTRLR1
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Name: SPORT control 1 register
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Size: 32 bits
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Address offset: 0x0008
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Read/write access: read/write
31 30
23 22
RX_SNK_LR_SW RX_SNK_BYTE_S
AP WAP
R/W R/W
15 14
RSVD
7 6
User Manual
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R/W 2'b00
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R/W 2'b00
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R/W 1'b0
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R/W 1'b1
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R/W 1'b0
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R/W 1'b0
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R/W 2'b00
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R/W 1'b0
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R/W 1'b0
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R/W 2'b00
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R/W 1'b0
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R/W 1'b0 1'b1: Self loopback mode
R/W 1'b0 1'b1: I
R/W 1'b0 1'b1: To be an I
R/W 1'b0 1'b1: To be an I
R/W 1'b0 1'b1: SCLK to Rx path (ADC path) is inverted.
R/W 1'b0 1'b1: SCLK to Tx path (DAC path) is inverted.
R/W 1'b0 1'b1: Reset SPORT module, remember to write 1 first and then write 0.
29 28
21 20
TX_SRC_LR_S TX_SRC_BYTE_S
WAP WAP
R/W R/W
13 12
CLEAR_RX_ER CLEAR_TX_ERR_
R_CNT CNT
R/W R/W
5 4
All information provided in this document is subject to legal disclaimers.
1'b1: LSB first
2'b00: L/R
2'b01: R/L
2'b10: L/L
2'b11: R/R @ DAC path
2'b00: OFF
2'b01: u law
2'b10: A law
1'b0: Tx is disabled
1'b1: Tx is started
1'b1: SPORT TX is disabled
1'b0: SPORT TX is enabled
1'b1: Internal loopback mode is enabled
1'b0: Internal loopback mode is disabled
1'b1: I 2 S/PCM bit clock is inverted
2
1'b0: I S/PCM bit clock is not inverted
2'b00: 16 bits
2'b10: 24 bits
2'b11: 8 bits
1'b1: Mono
1'b0: Stereo
1'b1: PCM negative mode
1'b0: PCM normal mode
2
3'b000: I S
3'b001: Left-Justified
3'b010: PCM mode A
3'b011: PCM mode B
3'b110: PCM mode A-N
3'b111: PCM mode B-N
1'b1: DSP and SPORT handshaking is enabled.
1'b0: GDMA and SPORT handshaking is enabled
2
S/PCM word clock is inverted
2 S or PCM slave (data path)
2
S or PCM slave (CLK path)
27 26
INT_ENABLE
R/W
19 18
RSVD
11 10
RSVD
3 2
390
Ameba-D User Manual
25 24
17 16
MODE_128FS MODE_40MHZ
R/W R/W
9 8
DEBUG_BUS_SEL
R/W
1 0
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