Realtek Ameba-D RTL872 D Series User Manual page 448

0 CSPL
20.3.4.2 LCDC_MCU_VSYNC_CFG

Name: LCDC MCU vertical synchronization register

Size: 32 bits

Address offset: 0x0064

Read/write access: read/write
31 30 29
15 14 13
MCUVSPD
R/W (SHW)
Bit Name
31:12 MCUVSPD
11:8 RSVD
7:0 MCUVSW
20.3.4.3 LCDC_MCU_TIMING_CFG

Name: LCDC MCU timing register

Size: 32 bits

Address offset: 0x0068

Read/write access: read/write
31 30 29
15 14 13
RDACTW
R/W (SHW)
Bit Name
31:21 RDINACTW
20:10 RDACTW
9:0 WRPULW
User Manual


R/W 0 The CS pulse polarity.


28 27 26 25
12 11 10 9
RSVD
Access Reset Description

R/W (SHW) 0


The maximum value is 1048571.
N/A 0 Reserved
R/W (SHW) 0 VSYNC signal width - 1. Unit: WR pulse width. (only for MCU VSYNC mode)
28 27 26 25
RDINACTW
R/W (SHW)
12 11 10 9
Access Reset Description
R/W (SHW) 0 RD inactive pulse width -1. Unit: system clock
R/W (SHW) 0 RD active pulse width -1. Unit: system clock
R/W (SHW) 2 Write clock divider depends on this value. The relationship between them is as
follows:





The frequency of write clock is derived from the following equation:
where WRPULW is any even value between 0 and 1022.
All information provided in this document is subject to legal disclaimers.
0: Low level for command address
1: High level for command parameter
0: Low level for active pulse
1: High level for active pulse
24 23 22
MCUVSPD
R/W (SHW)
8 7 6
MCUIFMODE = 1: VSYNC idle period. This value equals to VSYNC period –
IMAGEWIDTH * IMAGEHEIGHT * WR_pulse_per_pixel-5. Unit: WR pulse width.
MCUIFMODE = 0: The buffer time between frames. This value equals to the
time of a frame's end to the next start -5. Unit: WR pulse width.
MCUIFMODE = 2: Invalid usage.
24 23 22
8 7 6
0: The write clock divider is 2
2: The write clock divider is 4
4: The write clock divider is 6
6: The write clock divider is 8
...
Write clock = SYS_CLK/(WRPULW + 2)
448
Ameba-D User Manual
21 20 19 18
5 4 3 2
MCUVSW
R/W (SHW)
21 20 19 18
RDACTW
R/W (SHW)
5 4 3 2
WRPULW
R/W (SHW)
© REALTEK 2019. All rights reserved.
17 16
1 0
17 16
1 0