Realtek Ameba-D RTL872 D Series User Manual page 407

9:8 TMOD R/W
7 SCPOL R/W
6 SCPH R/W
5:4 FRF R/W
3:0 DFS R/W
DFS value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
User Manual
00 Transfer Mode. Relevant only when the SPI is configured as a serial-master device.
Selects the mode of transfer for serial communication. This field does not affect the
transfer duplicity. Only indicates whether the receive or transmit data are valid.
In transmit-only mode, data received from the external device is not valid and is not
stored in the receive FIFO memory; it is overwritten on the next transfer.
In receive-only mode, transmitted data are not valid. After the first write to the
transmit FIFO, the same word is retransmitted for the duration of the transfer.
In transmit-and-receive mode, both transmit and receive data are valid. The
transfer continues until the transmit FIFO is empty. Data received from the external
device are stored into the receive FIFO memory, where it can be accessed by the
host processor.
00 – Transmit & Receive
01 – Transmit Only
10 – Receive Only
0 Serial Clock Polarity. Valid when the frame format (FRF) is set to Motorola SPI. Used
to select the polarity of the inactive serial clock, which is held inactive when the SPI
master is not actively transferring data on the serial bus.
0 – Inactive state of serial clock is low
1 – Inactive state of serial clock is high
0 Serial Clock Phase. Valid when the frame format (FRF) is set to Motorola SPI. The
serial clock phase selects the relationship of the serial clock with the slave select
signal.
When SCPH = 0, data are captured on the first edge of the serial clock. When SCPH
= 1, the serial clock starts toggling one cycle after the slave select line is activated,
and data are captured on the second edge of the serial clock.
0 – Serial clock toggles in middle of the first data bit
1 – Serial clock toggles at start of the first data bit
00 Frame Format. Selects which serial protocol transfers the data.
00 – Motorola SPI
Other – Reserved
0111 Data Frame Size. Selects the data frame length. When the data frame size is
programmed to be less than 16 bits, the receive data are automatically right-
justified by the receive logic, with the upper bits of the receive FIFO zero-padded.
You must right-justify transmit data before writing into the transmit FIFO. The
transmit logic ignores the upper unused bits when transmitting the data. For the
field decode, refer to Table 19-2.
Table 19-2 DFS decode
Description
Reserved – undefined operation
Reserved – undefined operation
Reserved – undefined operation
4-bit serial data transfer
5-bit serial data transfer
6-bit serial data transfer
7-bit serial data transfer
8-bit serial data transfer
9-bit serial data transfer
10-bit serial data transfer
11-bit serial data transfer
12-bit serial data transfer
13-bit serial data transfer
14-bit serial data transfer
15-bit serial data transfer
16-bit serial data transfer
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407
Serial Peripheral Interface (SPI)
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