Realtek Ameba-D RTL872 D Series User Manual page 201

CK_PSC
CEN
Timer clock=CK_CNT
Counter register
Update event (UEV)
Prescaler control
register
Prescaler buffer
Prescaler counter
In upcounting mode, the counter counts from 0 to the auto-reload value (the content of the TIMx_ARR register), then restarts from 0 and
generates a counter overflow event.
Setting the UG bit in the TIMx_EGR register by software also generates an update event.
The update event can be disabled by software by setting the UDIS bit in the TIMx_CR register. This is to avoid updating the shadow registers
while writing new values to the preload registers. No update event occurs until the UDIS bit has been written to 0. However, the counter restarts
from 0, as well as the counter of the prescaler, but the prescale rate doesn't change. In addition, if the URS bit in the TIMx_CR register is set,
setting the UG bit generates an update event but without setting the UIF flag, thus no interrupt is sent. This is to avoid generating both update
and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (the UIF bit in TIMx_SR) is set depending on the URS bit:

The auto-reload shadow register is updated with the preload value (TIMx_ARR).

The buffer of the prescaler is reloaded with the preload value (the content of the TIMx_PSC register)
Fig 10-8 to Fig 10-13 show some examples of the counter behavior for different clock frequencies when the ARR field equals to 0x36.
User Manual
F8 F9
F7
0
Write a new value in TIMx_PSC
0
F7
Fig 10-7 Counter timing diagram with prescaler division change from 1 to 4
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FA FB FC
0 1
201
00 01
3
3
2 3 0 1 2
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General Timers
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