Realtek Ameba-D RTL872 D Series User Manual page 399

Ameba-D support high speed SPI slave. When SPI is configured as a slave device, the maximum frequency of the bit-rate clock (sclk_in)
provided by serial master can reach up to one-half the frequency of ssi_clk.
A summary of the frequency ratio restrictions between the bit-rate clock (sclk_out/sclk_in) and the SPI peripheral clock (ssi_clk) are described
as:

Master: Fssi_clk >= 2 × (maximum Fsclk_out)

Slave: Fssi_clk >= 2 × (maximum Fsclk_in)
The F of SPI0 is 100MHz. The F
ssi_clk
19.2.1.3 Transmit and Receive FIFO Buffers
The depth of both transmit and receive FIFO buffers is 64. The width is fixed at 16 bits due to the serial specifications, which state that a serial
transfer (data frame) can be 4 to 16 bits in length. Each data entry in the FIFO buffers contains a single data frame.
Note: The transmit and receive FIFO buffers are cleared when the SPI is disabled (SSI_EN = 0) or when it is reset.
The transmit FIFO is loaded by APB write commands to the SPI data register (DR). Data are popped (removed) from the transmit FIFO by the
shift control logic into the transmit shift register. The transmit FIFO generates a FIFO empty interrupt request (ssi_txe_intr) when the number
of entries in the FIFO is less than or equal to the FIFO threshold value. The threshold value, set through the programmable register TXFTLR,
determines the level of FIFO entries at which an interrupt is generated. The threshold value allows you to provide early indication to the
processor that the transmit FIFO is nearly empty. A transmit FIFO overflow interrupt (ssi_txo_intr) is generated if you attempt to write data
into an already full transmit FIFO.
Data are popped from the receive FIFO by APB read commands to the SPI data register (DR). The receive FIFO is loaded from the receive shift
register by the shift control logic. The receive FIFO generates a FIFO-full interrupt request (ssi_rxf_intr) when the number of entries in the FIFO
is greater than or equal to the FIFO threshold value plus 1. The threshold value, set through programmable register RXFTLR,
determines the level of FIFO entries at which an interrupt is generated.
The threshold value allows you to provide early indication to the processor that the receive FIFO is nearly full. A receive FIFO overrun interrupt
(ssi_rxo_intr) is generated when the receive shift logic attempts to load data into a completely full receive FIFO. However, this newly received
data are lost. A receive FIFO underflow interrupt (ssi_rxu_intr) is generated if you attempt to read from an empty receive FIFO. This alerts the
processor that the read data are invalid.
19.2.1.4 SPI Interrupts
The SPI supports combined and individual interrupt requests, each of which can be masked. The combined interrupt request is the ored result
of all other SPI interrupts after masking. The system designer has the choice of routing individual interrupt requests or only the combined
interrupt request to the Interrupt Controller. The SPI interrupts are described as follows:

Transmit FIFO Empty Interrupt (ssi_txe_intr) – Set when the transmit FIFO is equal to or below its threshold value and requires service to
prevent an under-run. The threshold value, set through a software-programmable register, determines the level of transmit FIFO entries
at which an interrupt is generated. This interrupt is cleared by hardware when data are written into the transmit FIFO buffer, bringing it
over the threshold level.

Transmit FIFO Overflow Interrupt (ssi_txo_intr) – Set when an APB access attempts to write into the transmit FIFO after it has been
completely filled. When set, data written from the APB is discarded. This interrupt remains set until you read the transmit FIFO overflow
interrupt clear register (TXOICR).
User Manual
Fig 19-7 Maximum sclk_out/ssi_clk Ratio
of SPI1 is 50MHz.
ssi_clk
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Serial Peripheral Interface (SPI)
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