Realtek Ameba-D RTL872 D Series User Manual page 21

Fig 20-23 LED control diagram ......................................................................................................................................................... 433
Fig 20-24 LED color mapping: single color and single channel ........................................................................................................ 433
Fig 20-25 LED color capping: single color and two channels ........................................................................................................... 434
Fig 20-26 LED color mapping: two colors and single channel .......................................................................................................... 434
Fig 20-27 LED color mapping: two colors and two channels ........................................................................................................... 435
Fig 20-28 LED color mapping: three colors and single channel ....................................................................................................... 435
Fig 20-29 LED color mapping: three colors and two channels ......................................................................................................... 436
Fig 21-1 Q-Decoder application scenario ......................................................................................................................................... 453
Fig 21-2 Quadrature signal ............................................................................................................................................................... 454
Fig 21-3 Q-Decoder block diagram .................................................................................................................................................. 454
Fig 21-4 Quadrature decoder phase state ....................................................................................................................................... 455
Fig 21-5 Position count state when CNT_SC = 0 .............................................................................................................................. 455
Fig 21-6 Position count state when CNT_SC = 1 .............................................................................................................................. 456
Fig 21-7 Position counter reset on index pulse (forward direction) ................................................................................................ 456
Fig 21-8 Position counter reset on index pulse (reverse direction) ................................................................................................. 456
Fig 21-9 IDX_INV = 0, position counter reset on (PHA, PHB) = (1, 0) ............................................................................................... 457
Fig 21-10 IDX_INV = 1, position counter reset on (PHA, PHB) = (1, 0) ............................................................................................. 457
Fig 21-11 Auto-index mechanism when IDX_INV = 0 ...................................................................................................................... 458
Fig 21-12 Auto-index mechanism when IDX_INV = 1 ...................................................................................................................... 458
Fig 21-13 Rotation count when RC_MOD = 1 .................................................................................................................................. 459
Fig 21-14 Velocity measurement unit timing flow ........................................................................................................................... 460
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Fig 22-1 I S mono/stereo audio-out interface configuration ........................................................................................................... 472
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Fig 22-2 I S 5.1 channel audio-out interface configuration ............................................................................................................. 473
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Fig 22-3 Signal lines in I S data format ............................................................................................................................................. 473
Fig 22-4 Transmitter as the master .................................................................................................................................................. 474
Fig 22-5 Receiver as the master ....................................................................................................................................................... 474
Fig 22-6 Controller as the master .................................................................................................................................................... 475
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Fig 22-7 I S Philips standard ............................................................................................................................................................. 475
Fig 22-8 Left-justified standard ........................................................................................................................................................ 476
Fig 22-9 Right-justified standard ...................................................................................................................................................... 476
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Fig 22-10 I S clock tree ..................................................................................................................................................................... 477
Fig 22-11 Memory block .................................................................................................................................................................. 478
Fig 22-12 FIFO allocation of mono channel (sample bit = 16-bit) .................................................................................................... 479
Fig 22-13 FIFO allocation of mono channel (sample bit = 32-bit) .................................................................................................... 479
Fig 22-14 FIFO allocation of stereo channel (sample bit = 16-bit) ................................................................................................... 480
Fig 22-15 FIFO allocation of stereo channel (sample bit = 24-bit) ................................................................................................... 480
Fig 22-16 FIFO allocation of stereo channel (sample bit = 32-bit) ................................................................................................... 481
Fig 22-17 FIFO allocation of 5.1 channel (sample bit = 16-bit) ........................................................................................................ 481
Fig 22-18 FIFO allocation of 5.1 channel (sample bit = 24-bit) ........................................................................................................ 482
Fig 22-19 FIFO allocation of 5.1 channel (sample bit = 32-bit) ........................................................................................................ 482
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List of Figures
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