Realtek Ameba-D RTL872 D Series User Manual page 269

7 M_RX_DONE
6 M_TX_ABRT
5 M_RD_REQ
4 M_TX_EMPTY
3 M_TX_OVER
2 M_RX_FULL
1 M_RX_OVER
0 M_RX_UNDER
13.3.2.14 IC_RAW_INTR_STAT

Name: I 2 C Raw Interrupt Status Register

Size: 32 bits

Address offset: 0x34

Read/write access: read-only
Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the I
31 30
23 22
15 14
DMA_I2C_DONE MS_CODE_DET
R R
7 6
RX_DONE TX_ABRT
R R
Bit Name
31:16 RSVD
15 DMA_I2C_DONE
14 MS_CODE_DET
13 RSVD
12 ADDR_MATCH
11 GEN_CALL
10 START_DET
9 STOP_DET
8 ACTIVITY
7 RX_DONE
User Manual
R/W 0x0
R/W 0x0
R/W 0x0
R/W 0x0
R/W 0x0
R/W 0x0
R/W 0x0
R/W 0x0
29
21
13
ADDR_MATCH
RSVD
5
RD_REQ
R
Access Reset Description
N/A - Reserved
R 0x0 Set when DMA operation is finished.
R 0x0 Indicates whether Master code is indicated in HS mode.
N/A - Reserved
R 0x0 Set when slave address is matched in low power mode
R 0x0 Set only when a General Call address is received and it is acknowledged. It stays set until it is
cleared either by disabling I
I 2 C stores the received data in the Rx buffer.
R 0x0 Indicates whether a START or RESTART condition has occurred on the I
of whether I
Indicates whether a STOP condition has occurred on the I
R 0x0
I 2 C is operating in slave or master mode.
Note: There is no status bit for a RESTART condition because it is detected as a normal start
condition. The I
conditions start from the IDLE state and send the message to all the slaves on the bus.
R 0x0 This bit captures I

Disabling the I

Reading the IC_CLR_ACTIVITY register

Reading the IC_CLR_INTR register

System reset
Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the
2
I C module is idle, this bit remains set until cleared, indicating that there was activity on the
bus.
When the I 2
R 0x0
acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating
that the transmission is done.
All information provided in this document is subject to legal disclaimers.
28 27
RSVD
20 19
RSVD
12 11
GEN_CALL
R R
4 3
TX_EMPTY TX_OVER
R R
2 C or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register.
2
C is operating in slave or master mode.
2 C protocol does not care whether it is a START or RESTART because both
2 C activity and stays set until it is cleared. There are four ways to clear it.
2 C
C is acting as a slave-transmitter, this bit is set to 1 if the master does not
269
Inter-integrated Circuit (I2C) Interface
2 C.
26 25
18 17
10 9
START_DET STOP_DET
R R
2 1
RX_FULL RX_OVER
R R
2 C interface regardless
2 C interface regardless of whether
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24
16
8
ACTIVITY
R
0
RX_UNDER
R