Realtek Ameba-D RTL872 D Series User Manual page 414

5 MSTIS/FAEIS R
4 RXFIS R
3 RXOIS R
2 RXUIS R
1 TXOIS R
0 TXEIS R
19.3.2.13 RISR

Name: Raw Interrupt Status Register

Size: 8 bits

Address offset: 0x34

Read/write access: read
This read-only register reports the status of the SPI interrupts prior to masking.
31 30
7 6
SSRIR TXUIR
R R
Bit Name Access
31:8 RSVD N/A
7 SSRIR R
6 TXUIR R
5 MSTIR/FAEIR R
User Manual
1 – ssi_txu_intr interrupt is active after masking
0 When SPI is configured as serial-master, this bit field is present as Multi-Master Contention
Interrupt Status.
0 – ssi_mst_intr interrupt is not active after masking
1 – ssi_mst_intr interrupt is active after masking
When SPI is configured as serial-slave, this bit field is present as Frame Alignment Interrupt
Status.
0 – ssi_fae_intr interrupt not active after masking
1 – ssi_fae_intr interrupt is active after masking
0 Receive FIFO Full Interrupt Status.
0 – ssi_rxf_intr interrupt is not active after masking
1 – ssi_rxf_intr interrupt is full after masking
0 Receive FIFO Overflow Interrupt Status.
0 – ssi_rxo_intr interrupt is not active after masking
1 – ssi_rxo_intr interrupt is active after masking
0 Receive FIFO Underflow Interrupt Status.
0 – ssi_rxu_intr interrupt is not active after masking
1 – ssi_rxu_intr interrupt is active after masking
0 Transmit FIFO Overflow Interrupt Status.
0 – ssi_txo_intr interrupt is not active after masking
1 – ssi_txo_intr interrupt is active after masking
0 Transmit FIFO Empty Interrupt Status.
0 – ssi_txe_intr interrupt is not active after masking
1 – ssi_txe_intr interrupt is active after masking
29
5 4
MSTIR/FAEIR RXFIR
R R
Reset Description
- Reserved
0 SS_N Rising Edge Detect Raw Interrupt Status. This bit field is present only if the SPI is configured
as a serial-slave device.
0 – ssi_ssr_intr interrupt is not active prior to masking
1 – ssi_ssr_intr interrupt is active prior to masking
0 Transmit FIFO Under Flow Raw Interrupt Status. This bit field is present only if the SPI is
configured as a serial-slave device.
0 – ssi_txu_intr interrupt is not active prior to masking
1 – ssi_txu_intr interrupt is active prior to masking
0 When SPI is configured as serial-master, this bit field is present as Multi-Master Contention Raw
Interrupt Status.
0 – ssi_mst_intr interrupt is not active prior to masking
1 – ssi_mst_intr interrupt is active prior to masking
When SPI is configured as serial-slave, this bit field is present as Frame Alignment Error Raw
Interrupt Status.
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... 10
RSVD
3 2
RXOIR RXUIR
R R
414
Ameba-D User Manual
9 8
1 0
TXOIR TXEIR
R R
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