Realtek Ameba-D RTL872 D Series User Manual page 365

0x56 [12:0] DAC_L_BIQUAD_B1_5[28:16]
[15:13] RSVD
17.6.3.24 0x57 ~ 0x58
Address Bit Name
0x57 [15:0] DAC_L_BIQUAD_B2_5[15:0]
0x58 [12:0] DAC_L_BIQUAD_B2_5[28:16]
[15:13] RSVD
17.6.3.25 0x59 ~ 0x5A
Address Bit Name
0x59 [15:0] DAC_L_BIQUAD_A1_5[15:0]
0x5A [12:0] DAC_L_BIQUAD_A1_5[28:16]
[15:13] RSVD
17.6.3.26 0x5B ~ 0x5C
Address Bit Name
0x5B [15:0] DAC_L_BIQUAD_A2_5[15:0]
0x5C [12:0] DAC_L_BIQUAD_A2_5[28:16]
[13] DAC_L_BIQUAD_EN_5
[14] DAC_L_BIQUAD_WCLR_5
[15] DAC_L_BIQUAD_STATUS_5
17.6.3.27 0x5D
Address Bit Name
0x5D [0] DAC_R_BQ_EQ_PARAM_UPDATE
[1] DAC_R_BQ_EQ_CD_EN
[3:2] DAC_R_BQ_EQ_DITHER_SEL
[4] RSVD
[5] DAC_R_BQ_EQ_CD_FLAG
User Manual
R/W 13'h0
N/A 3'b000
Access Reset
R/W 16'h0
R/W 13'h0
N/A 3'b000
Access Reset
R/W 16'h0
R/W 13'h0
N/A 3'b000
Access Reset Description
R/W 16'h0 DAC Lch EQ 5th-band coefficient a2
2's complement in 4.25 format, which means that the
R/W 13'h0
range is from –8~7.99.
R/W 1'b0 DAC Lch 5th-band EQ Biquad control


W 1'b0 DAC Lch 5th-band Biquad filter write clear


Write "1" to send clear status pulse
R 1'b0 DAC Lch 5th-band Biquad filter status


Access Reset
R/W 1'b1
R/W 1'b1
R/W 2'b00
N/A 1'b0
R
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365
2's complement in 4.25 format, which means that
the range is from –8~7.99.
Reserved
Description
DAC Lch EQ 5th-band coefficient b2
2's complement in 4.25 format, which means that
the range is from –8~7.99.
Reserved
Description
DAC Lch EQ 5th-band coefficient a1
2's complement in 4.25 format, which means that
the range is from –8~7.99.
Reserved
1'b0: Disable
1'b1: Enable
1'b0: Normal
1'b1: Overflow
1'b0: Normal
1'b1: Overflow
Description
DAC Rch EQ

1'b0: Busy (Waiting for cross)

1'b1: Stand-by
Write "1" to send parameter update pulse
DAC Rch EQ cross detection control

1'b0: Disable (Test mode)

1'b1: Enable (Normal mode)
DAC Rch EQ dither control

2'b00: Normal

2'b01: LSB

2'b10: {LSB+1, LSB}

2'b11: {LSB+2, LSB+1, LSB}
Reserved
DAC Rch Biquad filter cross detect status
Audio Codec (AC)
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