Realtek Ameba-D RTL872 D Series User Manual page 264

13.3.2.3 IC_SAR

Name: I 2 C Slave Address Register

Size: 32 bits

Address offset: 0x08

Read/write access: read/write
31 30 29
Bit Name Access
31:10 RSVD N/A
9:0 IC_SAR R/W
Note: It is not necessary to perform any write to this register if I
13.3.2.4 IC_HS_MADDR

Name: I 2 C High Speed Master Mode Code Address Register

Size: 32 bits

Address offset: 0x0C

Read/write access: read/write
31 30
Bit Name Access
31:3 RSVD N/A
2:0 IC_HS_MAR R/W
Note: It is not necessary to perform any write to this register if I
13.3.2.5 IC_DATA_CMD

Name: I 2 C Rx/Tx Data Buffer and Command Register

Size: 32 bits

Bit[11:8] exists if DMA_MODE = 0

Address offset: 0x10

Read/write access: read/write
This is the register the CPU writes to when filling the Tx FIFO and the CPU reads from when retrieving bytes from Rx FIFO.
Note: In order for the I 2 C to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise
the I 2 C will stop acknowledging.
User Manual
... 12 11
RSVD
Reset Description
- Reserved
0x11 The IC_SAR holds the slave address when the I
only IC_SAR[6:0] is used.
This register can be written only when the I
IC_ENABLE register being set to 0. Writes at other times have no effect.
Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07,
or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the
IC_SAR or IC_TAR to a reserved value.
29 ...
RSVD
Reset Description
- Reserved
0x0 This bit field holds the value of the I
reserved 8-bit codes (00001xxx) that are not used for slave addressing or other purposes. Each
master has its unique master code; up to eight high speed mode masters can be present on
2
the same I C bus system. Valid values are from 0 to 7.
This register can be written only when the I
IC_ENABLE register being set to 0. Writes at other times have no effect.
All information provided in this document is subject to legal disclaimers.
10 9 8
2
2
C interface is disabled, which corresponds to the
2 C is enabled as an I 2 C master only.
5 4 3
2 C HS mode master code. HS-mode master codes are
2 C interface is disabled, which corresponds to the
2 2
C is enabled as an I C slave only.
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Ameba-D User Manual
7 ... 2
IC_SAR
R/W
C is operating as a slave. For 7-bit addressing,
2 1
IC_HS_MAR
R/W
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