Realtek Ameba-D RTL872 D Series User Manual page 402

The Slave uses the sclk_out signal from the master as a strobe in order to drive rxd signal data onto the serial bus. Routing and sampling delays
on the sclk_out signal by the slave device can mean that the rxd bit has not stabilized to the correct value before the master samples the rxd
signal. Fig 19-9 shows an example of how a routing delay on the rxd signal can result in an incorrect rxd value at the default time when the
master samples the port.
When the RXD Sample Delay logic is included, the user can dynamically program a delay value in order to move the sampling time of the rxd
signal equal to a number of ssi_clk cycles from the default.
The sample delay logic has a resolution of one ssi_clk cycle. Software can "train" the serial bus by coding a loop that continually reads from the
slave and increments the master's RXD Sample Delay value until the correct data is received by the master.
19.2.3.1.2 Data Transfers
Data transfers are started by the serial-master device. When the SPI is enabled (SSI_EN=1), at least one valid data entry is present in the
transmit FIFO and a serial-slave device is selected. When actively transferring data, the busy flag (BUSY) in the status register (SR) is set. You
must wait until the busy flag is cleared before attempting a new serial transfer.
Note: The BUSY status is not set when the data are written into the transmit FIFO. This bit gets set only when the target slave has been
selected and the transfer is underway. After writing data into the transmit FIFO, the shift logic does not begin the serial transfer until a positive
edge of the sclk_out signal is present. The delay in waiting for this positive edge depends on the baud rate of the serial transfer. Before polling
the BUSY status, you should first poll the TFE status (waiting for 1) or wait for BAUDR * ssi_clk clock cycles.
19.2.3.1.3 Master SPI Serial Transfers
When the transfer mode is "transmit and receive" or "transmit only" (TMOD = 2'b00 or TMOD = 2'b01, respectively), transfers are terminated
by the shift control logic when the transmit FIFO is empty. For continuous data transfers, you must ensure that the transmit FIFO buffer does
not become empty before all the data have been transmitted. The transmit FIFO threshold level (TXFTLR) can be used to early interrupt
(ssi_txe_intr) the processor indicating that the transmit FIFO buffer is nearly empty.
When a DMA is used for APB accesses, the transmit data level (DMATDLR) can be used to early request (dma_tx_req) the DMA Controller,
indicating that the transmit FIFO is nearly empty. The FIFO can then be refilled with data to continue the serial transfer. The user may also
write a block of data (at least two FIFO entries) into the transmit FIFO before enabling a serial slave. This ensures that serial transmission does
not begin until the number of data-frames that make up the continuous transfer are present in the transmit FIFO.
When the transfer mode is "receive only" (TMOD = 2'b10), a serial transfer is started by writing one "dummy" data word into the transmit FIFO
when a serial slave is selected. The txd output from the SPI is held at a constant logic level for the duration of the serial transfer. The transmit
FIFO is popped only once at the beginning and may remain empty for the duration of the serial transfer. The end of the serial transfer is
controlled by the "number of data frames" (NDF) field in control register 1 (CTRLR1).
If, for example, you want to receive 24 data frames from a serial-slave peripheral, you should program the NDF field with the value 23; the
receive logic terminates the serial transfer when the number of frames received is equal to the NDF value + 1. This transfer mode increases the
bandwidth of the APB bus as the transmit FIFO never needs to be serviced during the transfer. The receive FIFO buffer should be read each
time the receive FIFO generates a FIFO full interrupt request to prevent an overflow.
The receive FIFO threshold level (RXFTLR) can be used to give early indication that the receive FIFO is nearly full. When a DMA is used for APB
accesses, the receive data level (DMARDLR) can be used to early request (dma_rx_req) the DMA Controller, indicating that the receive FIFO is
nearly full.
A typical software flow for completing an SPI serial transfer from the SPI serial master is outlined as follows:
(1) If the SPI is enabled, disable it by writing 0 to the SSI Enable register (SSIENR).
(2) Set up the SPI control registers for the transfer; these registers can be set in any order.

Write Control Register 0 (CTRLR0). For SPI transfers, the serial clock polarity and serial clock phase parameters must be set identical
to target slave device.

If the transfer mode is receive only, write Control Register 1 (CTRLR1) with the number of frames in the transfer minus 1; for
example, if you want to receive four data frames, write this register with 3.

Write the Baud Rate Select Register (BAUDR) to set the baud rate for the transfer.

Write the Transmit and Receive FIFO Threshold Level registers

Write the IMR register to set up interrupt masks.
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(TXFTLR and RXFTLR, respectively) to set FIFO threshold levels.
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Ameba-D User Manual
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