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Ameba-D RTL8722DM-EVB
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Manuals and User Guides for Realtek Ameba-D RTL8722DM-EVB. We have
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Realtek Ameba-D RTL8722DM-EVB manual available for free PDF download: User Manual
Realtek Ameba-D RTL8722DM-EVB User Manual (494 pages)
Brand:
Realtek
| Category:
Motherboard
| Size: 23.22 MB
Table of Contents
Table of Contents
4
Contents
4
List of Tables
12
List of Figures
17
Conventions
22
Fig 1-1 System Architecture
23
General Description
23
Product Overview
23
System Architecture
23
Introduction
25
KM4 Memory Map and Register Boundary Addresses
25
Memory Organization
25
KM0 Memory Map and Register Boundary Addresses
26
KM0 Embedded SRAM
27
KM4 Embedded SRAM
27
KM4 Extension SRAM
27
Psram
27
Retention SRAM
27
SPI Flash Memory
27
Memory Protection Unit (MPU)
28
Mpu_Type
28
Register Field Description
28
Register Map
28
Mpu_Ctrl
29
Mpu_Rbar
30
Mpu_Rnr
30
Mpu_Rlar
31
Mpu_Rbar_A<N
32
Mpu_Rlar_A<N
32
Mpu_Mair0
33
Memory Attribute Indirection Register Attributes (MAIR_ATTR)
34
Mpu_Mair1
34
Inner
35
Outer
35
Features
36
Nested Vectored Interrupt Controller (NVIC)
36
NVIC Diagram
36
NVIC Table
36
NVIC Register Description
38
ISER0 and ISER1
39
IABR0 and IABR1
40
ICER0 and ICER1
40
ICPR0 and ICPR1
40
Ipr0 ~ Ipr14
40
ISPR0 and ISPR1
40
Stir
40
CPU System Tick (Systick) Timer
42
Features
42
Functional Description
42
Register Description
42
Syst_Csr
42
Syst_Cvr
43
Syst_Rvr
43
Syst_Calib
44
Features
45
Fig 6-1 Pad Diagram
45
Functional Description
45
Pad Control and Pinmux
45
Pad Types
45
Pad Pull Resistor Control
46
Audio Pad
47
I 2 C Open-Drain Mode
47
Pad Driving Strength
47
Pad Schmitt Trigger
47
Pad Shut down
47
Pin Multiplexing Function
48
Fig 6-2 Selecting an Alternate Function on Ameba-D
49
Register − PADCTRL
49
Architecture Block Diagram
51
Core-To-Core Interrupt
51
Features
51
Fig 7-1 IPC System Architecture
51
Functional Description
51
Inter Processor Communication (IPC)
51
Fig 7-2 IPC Interrupt Request
52
Fig 7-3 IPC Hardware Semaphore Mechanism
52
Hardware Semaphore
52
IPC Registers
53
Ipcx_Ier
53
Ipcx_Icr
54
Ipcx_Idr
54
Ipcx_Irr
54
Ipc0_Cpuid
55
Ipc0_Sem
55
Ipcx_Isr
55
Ipcx_Ier_R
56
Ipc_Usr
57
Features
58
Fig 8-1 Block Diagram
58
Functional Description
58
General Product Description
58
General Purpose Input/Output (GPIO)
58
Introduction
58
Data and Control Flow
59
Fig 8-2 Control RTL Block Diagram
59
Fig 8-3 Read Back of External Gpio_Ext_Portx Data Timing
61
Interrupts
61
Fig 8-4 Interrupt RTL Block Diagram
62
Fig 8-5 Debounce RTL Diagram
62
Fig 8-6 Debounce Timing with Asynchronous Reset Flip-Flops
63
Fig 8-7 Synchronization and Edge Detect Interrupt Generation When GPIO_INT_BOTH_EDGE=0
64
Fig 8-8 Interrupt Edge Detection and Interrupt Clear Timing When GPIO_SYNC_PA_INTERRPUTS = 1 (Metastability Included)
64
Fig 8-9 Interrupt Edge Detection and Interrupt Clear Timing When GPIO_SYNC_PA_INTERRPUTS = 0 (Metastability Removed)
65
Fig 8-10 Write to Interrupt Clear Register, Coincident with Detection of New Interrupt
66
Fig 8-11 Synchronization and Edge Detect Interrupt Generation When GPIO_INT_BOTH_EDGE=0
66
Fig 8-12 Interrupt Edge Detection and Interrupt Clear Timing When GPIO_SYNC_PA_INTERRPUTS = 1 and GPIO_INT_BOTH_EDGE=1 (Metastability Included)
67
Fig 8-13 Interrupt Edge Detection and Interrupt Clear Timing When GPIO_SYNC_PA_INTERRPUTS = 0 and
68
Fig 8-14 Level-Sensitive Interrupt RTL Diagram
68
Bus Interface
69
Fig 8-15 Active-Low Level-Sensitive Interrupt Generation Timing
69
Fig 8-16 Relationship between APB and APB Slave Data Widths
69
Registers
69
Register Memory Map
70
Register and Field Descriptions
71
Programming Considerations
85
Programming the GPIO
85
Software Registers
85
Direct Memory Access Controller (DMAC)
86
Fig 9-1 Block Diagram of DMAC
86
General Product Description
86
Product Overview
86
Fig 9-2 Peripheral-To-Peripheral DMA Transfer on the same AHB Layer
87
Basic Definitions
88
Fig 9-3 Peripheral-To-Memory DMA Transfer on Separate AHB Layers
88
Fig 9-4 DMA Transfer Hierarchy for Non-Memory Peripherals
89
Fig 9-5 DMA Transfer Hierarchy for Memory
89
Features
90
Block Flow Controller and Transfer Type
92
Functional Description
92
Setup/Operation of DMA Transfers
92
Basic Interface Definitions
93
Handshaking Interface
93
Handshaking Interface - Peripheral Is Not Flow Controller
94
Memory Peripherals
94
Fig 9-7 Burst Transaction - Pclk = Hclk
96
Fig 9-10 Burst Followed by Back-To-Back Single Transactions
98
Fig 9-12 Burst Transaction Ignored During Active Single Transaction
99
Fig 9-13 Generation of Dma_Req and Dma_Single by Source
99
Handshaking Interface - Peripheral Is Flow Controller
100
Fig 9-15 Burst Transaction Followed by Single Transaction that Terminates Block
101
Fig 9-16 Single Transaction Followed by Burst Transaction that Terminates Block
102
Fig 9-9 Single Transaction
102
Setting up Transfers
102
Fig 9-17 Breakdown of Block Transfer
104
Fig 9-24 Breakdown of Block Transfer
108
Fig 9-26 Source FIFO Contents Where Watermark Level Is Dynamically Adjusted
109
Fig 9-27 Block Transfer to Destination
110
Fig 9-28 Block Transfer up to Time 'T4
112
Fig 9-30 FIFO Status after Early-Terminated Burst
113
Fig 9-31 Data Loss When Pre-Fetching Is Enabled
114
Fig 9-32 Timing Exception on Dma_Finish to Source Peripheral
115
Fig 9-33 Case of no Data Loss When Pre-Fetching Is Enabled
116
Fig 9-36 Data Loss When Data Pre-Fetching Is Disabled
119
Fig 9-37 Transaction Request through Peripheral Interrupt
120
Flow Control Configurations
120
Fig 9-38 Flow Control Configurations
121
Peripheral Burst Transaction Requests
121
Fig 9-41 SSI Receive FIFO
124
Generating Requests for the AHB Master Bus Interface
125
Arbitration for AHB Master Interface
127
Fig 9-42 Arbitration Flow for Master Bus Interface
127
Scatter/Gather
128
Fig 9-43 Example of Destination Scatter Transfer
129
Fig 9-44 Source Gather When SGR.SGI = 0X1
129
AHB Transfer Error Handling
130
Endianness
130
Register Memory Map
131
Registers
131
Registers and Field Descriptions
136
Programming the DMAC
170
DMA Transfer Types
171
Illegal Register Access
171
Register Access
171
Fig 9-45 Multi-Block Transfer Using Linked Lists When Dmah_Chx_Stat_Src Set to True
172
Fig 9-46 Multi-Block Transfer Using Linked Lists When Dmah_Chx_Stat_Src Set to False
173
Fig 9-47 Mapping of Block Descriptor (LLI) in Memory to Channel Registers When Dmah_Chx_Stat_Src Set to True
173
Fig 9-48 Mapping of Block Descriptor (LLI) in Memory to Channel Registers When Dmah_Chx_Stat_Src Set to False
173
Programing Example
176
Fig 9-49 Flowchart for DMA Programming Example
177
Programming a Channel
178
Fig 9-50 Multi-Block with Linked Address for Source and Destination
181
Fig 9-51 Multi-Block with Linked Address for Source and Destination Where Sarx and Darx between Successive Blocks Are
181
Fig 9-52 DMA Transfer Flow for Source and Destination Linked List Address
182
Fig 9-53 Multi-Block DMA Transfer with Source and Destination Address Auto-Reloaded
183
Fig 9-54 DMA Transfer Flow for Source and Destination Address Auto-Reloaded
184
Fig 9-55 Multi-Block DMA Transfer with Source Address Auto-Reloaded and Linked List Destination Address
186
Fig 9-56 DMA Transfer Flow for Source Address Auto-Reloaded and Linked List Destination Address
187
Fig 9-57 Multi-Block DMA Transfer with Source Address Auto-Reloaded and Contiguous Destination Address
189
Fig 9-58 DMA Transfer Flow for Source Address Auto-Reloaded and Contiguous Destination Address
189
Fig 9-59 Multi-Block DMA Transfer with Linked List Source Address and Contiguous Destination Address
191
Disabling a Channel Prior to Transfer Completion
192
Fig 9-60 DMA Transfer Flow for Source Address Auto-Reloaded and Contiguous Destination Address
192
Defined-Length Burst Support on DMAC
193
Basic Timer
194
Block Diagram
194
Features
194
Fig 10-1 Block Diagram
194
Functional Description
194
General Timers
194
Introduction
194
Features
195
Introduction
195
Pulse Mode Timer
195
Block Diagram
196
Fig 10-2 TIM4 Block Diagram
196
Functional Description
196
Fig 10-3 Statistic Pulse Width Mode Diagram (Positive Edge of TRGI Is Active for Capture)
197
Features
198
Fig 10-4 Statistic Pulse Number Mode Diagram (Positive Edge of TRGI Is Active for Capture, ARR=E6)
198
Introduction
198
PWM Mode Timer
198
Block Diagram
199
Fig 10-5 PWM Timer Block Diagram
199
Functional Description
199
Fig 10-10 Counter Timing Diagram (Internal Clock Divided by 4)
202
Fig 10-8 Counter Timing Diagram (Internal Clock Divided by 1)
202
Fig 10-9 Counter Timing Diagram (Internal Clock Divided by 2)
202
Fig 10-11 Counter Timing Diagram (Internal Clock Divided by N)
203
Fig 10-12 Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
203
Fig 10-13 Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
204
Fig 10-14 Edge-Aligned PWM Waveforms (ARR=8, Ccxp=0)
205
Fig 10-15 One-Pulse Mode Timing
205
Registers
206
TIM0/TIM1/TIM2/TIM3 Registers
206
TIM4 Registers
209
TIM5 Registers
213
Design Implementation
227
Fig 10-16 Block Diagram
227
Introduction
227
Fig 10-17 Synchronous Data Diagram
228
Operation Flow
228
Synchronous Data from Fast Clock to Slow Clock
228
Upcounting Mode
228
Pulse Mode
229
PWM Mode
229
Input Capture Mode
230
Block Diagram
231
Features
231
Fig 11-1 RTC Block Diagram
231
Introduction
231
Product Overview
231
Real-Time Clock (RTC)
231
Clock and Prescaler
232
Fig 11-2 RTC Prescale Diagram
232
Fig 11-3 RTC Clock Select Diagram
232
Functional Description
232
RTC Clock Select Diagram
232
Auto-Trigger Calibration Circuit
233
Fig 11-4 Calibration Block Diagram
233
Fig 11-5 Xtal_Req_32K Block Diagram
233
Digital Calibration
234
Programmable Alarm
234
Write Protection
234
Day Threshold Program
235
Registers
235
RTC Control Register (RTC_CR)
235
RTC Time Register (RTC_TR)
235
RTC Initialization and Status Register (RTC_ISR)
237
RTC Calibration Register (RTC_CALIBR)
238
RTC Prescaler Register (RTC_PRER)
238
RTC Alarm 1 Register High (RTC_ALMR1H)
239
RTC Alarm 1 Register Low (RTC_ALMR1L)
239
RTC 32K Auto-Calibration Register (RTC_CLKACALR)
240
RTC Write Protection Register (RTC_WPR)
240
Configure Alarm
241
Configure Calibration
241
Initialize the Calendar
241
Operation Flow
241
Daylight Saving Time
242
Features
243
Introduction
243
Registers
243
Watchdog Timer (WDT)
243
Functional Description
245
Inter-Integrated Circuit (I C) Interface
245
Introduction
245
Overview
245
Fig 13-1 Block Diagram of I C
246
I 2 C Terminology
246
Fig 13-2 Master/Slave and Transmitter/Receiver Relationships
247
I 2 C Behavior
247
Fig 13-3 Data Transfer on the I 2 C Bus
248
I 2 C Protocols
248
Fig 13-5 7-Bit Address Format
249
Fig 13-6 10-Bit Address Format
249
Fig 13-7 Master-Transmitter Protocol
250
Fig 13-8 Master-Receiver Protocol
251
Fig 13-12 IC_DATA_CMD Register Content
252
Fig 13-13 Master Transmitter - Tx FIFO Empties/Stop Generation
252
Tx FIFO Management and START, STOP and RESTART Generation
252
Fig 13-14 Master Receiver - Tx FIFO Empties/Stop Generation
253
Fig 13-17 Master Transmitter - Stop Bit of IC_DATA_CMD Set/Tx FIFO Not Empty
253
Fig 13-18 Master Receiver - Stop Bit of IC_DATA_CMD Set/Tx FIFO Not Empty
254
Fig 13-19 Multiple Master Arbitration
254
Multiple Master Arbitration
254
Clock Synchronization
255
Fig 13-20 Multi-Master Clock Synchronization
255
Operation Modes
255
IC_CLK Frequency Configuration
257
DMA Controller Interface
259
Programmable SDA Hold Time
259
Fig 13-21 I 2 C 8-Bit FIFO Content with Transfer Control Register
260
Low Power Mode
260
Register Memory Map
261
Registers
261
Registers and Field Descriptions
262
Block Diagram
284
Features
284
Fig 14-1 UART Block Diagram
284
Introduction
284
Universal Asynchronous Receiver/Transmitter (UART)
284
Register
285
Ier
286
Iir
286
Lcr
287
Mcr
288
Lsr
289
Msr
289
Scr
290
Rbr
291
Stsr
291
Thr
291
Miscr
292
Baud_Mon
293
Irda_Sir_Rx_Pw_Ctrl
293
Irda_Sir_Tx_Pw_Ctrl
293
Dbg_Uart
294
Reg_Rx_Path_Ctrl
294
Reg_Mon_Baud_Ctrl
295
Reg_Mon_Baud_Sts
295
Reg_Mon_Cyc_Num
295
Fcr
296
Reg_Rx_Byte_Cnt
296
Baud Rate Calculation
297
Design Implementation
297
Clock Structure of Rx Path
298
Fig 14-2 Clock Structure of KM0 Log UART Rx Path
298
Fig 14-3 Clock Structure of KM0 LUART Rx Path
299
Fig 14-4 Clock Structure of KM4 UART0 Rx Path
299
Irda_Sir_Encoder/Decoder
299
Auto-Flow Control
300
Fig 14-5 Relationship between Irda Signal and UART Signal
300
Fig 14-6 Signal Connection in Auto-Flow Control Mode
300
Interrupt Control
300
DMA Flow Control
301
Fig 14-7 DMA Interface Timing Diagram
301
Fig 14-8 DMA Interface Timing Diagram
301
Fig 15-1 IR Signal Model
302
Fig 15-2 IR Tx Flow
302
Infrared Radiation (IR)
302
Introduction
302
Overall Description
302
Architecture
303
Features
303
Fig 15-3 IR Rx Flow
303
Fig 15-4 IR Block Diagram
303
Glitch Filter
304
Interrupt
304
Registers
304
Scaler
304
IR Clock Control Register
305
IR Tx Registers
305
IR Rx Registers
308
IR Application Note
312
IR Version Register
312
RCU Application
312
Fig 15-5 Tx Output Level
313
Receiver Application
313
Application Scenario
314
Block Diagram
314
Features
314
Fig 16-1 Key-Scan Block Diagram
314
Functional Description
314
Key-Scan
314
Overall Description
314
Fig 16-2 Typical Application Setup with External Keypad
315
Work Principle
315
Fig 16-3 Key-Scan Flow
316
Fig 16-4 Key-Scan Timing
317
Fig 16-5 Difference of FIFO Items between Two Work Modes
317
Clock Configuration
318
FIFO Mechanism
318
Fig 16-6 FIFO Structure
318
Shadow Key Problem
319
Fig 16-8 4*3 Keypad Example
320
Fig 16-9 Shadow Key Condition
320
Fig 16-10 Correct Three-Key Condition
321
Ks_Clk_Div
321
Registers
321
Ks_Ctrl
322
Ks_Tim_Cfg0
322
Ks_Tim_Cfg1
322
Ks_Col_Cfg
323
Ks_Fifo_Cfg
323
Ks_Data_Num
324
Ks_Row_Cfg
324
Ks_Data
325
Ks_Imr
325
Ks_Icr
326
Ks_Isr
326
Ks_Dummy
327
Ks_Isr_Raw
327
Audio Codec (AC)
329
Diagram
329
Fig 17-1 Audio Codec Diagram
329
Introduction
329
Analog Part
330
Digital Part
330
Key Features
330
DAC Path
331
Specifications
331
ADC Path
332
Application and Implementation
333
Audio Output
333
Fig 17-2 Cap-Less Mode Connection with Headphone Jack
333
Audio Input
334
Fig 17-3 Differential Mode Connection with Headphone Jack
334
Fig 17-4 Single-End Mode Connection with Headphone Jack
334
Fig 17-5 Line-In Mode Connection
335
Fig 17-6 Analog MIC Single-End Mode Connection
335
Fig 17-7 Analog MIC Differential Mode Connection
335
Fig 17-10 Mono PDM Format
336
Fig 17-8 Digital MIC Mono Mode Connection
336
Fig 17-9 Digital MIC Stereo Mode Connection
336
Analog Part
337
Fig 17-11 Stereo PDM Format
337
Fig 17-12 I 2 S Acting as PDM
337
Registers
337
Digital Part
341
Dac_Eq
360
Adc_Eq
370
Architecture
381
Audio Codec Controller (ACC)
381
Block Diagram
381
Features
381
Fig 18-1 Ameba-D ACC + AC Architecture
381
Introduction
381
Data Part
382
Fig 18-2 ACC Block Diagram
382
Fig 18-3 I S Audio Data Format
385
Fig 18-4 Left-Justified Data Format
386
Fig 18-5 PCM Mode B Data Format
386
Fig 18-6 PCM Mode B-N Data Format
386
Fig 18-7 PCM Mode a Data Format
386
Control Part
387
Fig 18-8 PCM Mode A-N Data Format
387
Fig 18-9 si Write Timing
387
ACC Clock
388
Fig 18-10 si Read Timing
388
Fig 18-11 ACC Clock Architecture
388
Registers
388
SPORT Control Registers
388
Control Registers
393
Block Diagram
395
Features
395
Fig 19-1 SPI Block Diagram
395
Product Overview
395
Serial Peripheral Interface (SPI)
395
Functional Description
396
Overview
396
Fig 19-2 SPI Serial Format (SCPH = 0)
397
Fig 19-3 SPI Serial Format Continuous Transfers (SCPH = 0 and SS Toggling)
397
Fig 19-4 SPI Serial Format Continuous Transfers (SCPH = 0 and SS Not-Toggling)
397
Fig 19-5 SPI Serial Format (SCPH = 1)
398
Fig 19-6 SPI Serial Format Continuous Transfers (SCPH = 1)
398
Operation Modes
400
Transfer Modes
400
Fig 19-8 SPI Configured as Master Device
401
DMA Controller Interface
404
Register Memory Map
404
Registers
404
Registers and Field Descriptions
406
Features
421
Introduction
421
LCD Application Scenario
421
Liquid Crystal Display Controller (LCDC)
421
Overall Description
421
Architecture
422
Block Diagram
422
Fig 20-1 MCU I/F + LCM with GRAM
422
Fig 20-2 RGB I/F + LCM Without GRAM
422
Fig 20-3 LCDC Block Diagram
422
Fig 20-4 Two Data Paths
423
Fig 20-5 MCU I/O Mode Application Scenario
423
Fig 20-6 DMA Mode Application Scenario
424
Fig 20-7 MCU Interface
424
MCU Interface
424
Fig 20-10 MCU I/F Read Command Timing Parameters
425
Fig 20-8 MCU I/F Command Setting Timing Parameters
425
Fig 20-9 MCU I/F Data Writing Timing Parameters
425
Fig 20-11 MCU VSYNC Mode Timing
426
Fig 20-12 MCU te Mode Timing
426
Fig 20-13 MCU te Mode Frame Synchronization
426
Fig 20-14 8080 I/F 8-Bit Output
427
Fig 20-15 8080 I/F 16-Bit Output
427
RGB Interface
427
Fig 20-16 RGB Interface
428
Fig 20-18 RGB de Mode Timing
429
LED Control
430
Fig 20-21 LED Interface
431
Fig 20-22 LED Control Timing
432
Fig 20-24 LED Color Mapping: Single Color and Single Channel
433
Fig 20-25 LED Color Capping: Single Color and Two Channels
434
Fig 20-26 LED Color Mapping: Two Colors and Single Channel
434
Fig 20-27 LED Color Mapping: Two Colors and Two Channels
435
Fig 20-28 LED Color Mapping: Three Colors and Single Channel
435
Fig 20-29 LED Color Mapping: Three Colors and Two Channels
436
Pinmux
436
Supported Resolution
436
Registers
438
Global Control Registers
439
Interrupt and Status Registers
441
RGB Control Registers
444
MCU Control Registers
446
LED Control Registers
449
Image Control Registers
451
Programming the LCDC
451
RGB DMA Auto-Mode
451
MCU DMA Trigger-Mode
452
MCU I/O Mode
452
Application Scenario
453
Features
453
Fig 21-1 Q-Decoder Application Scenario
453
Introduction
453
Overall Description
453
Quadrature Decoder (Q-Decoder)
453
Architecture
454
Fig 21-2 Quadrature Signal
454
Fig 21-3 Q-Decoder Block Diagram
454
Q-Decoder Block Diagram
454
Fig 21-4 Quadrature Decoder Phase State
455
Position Measurement
455
Fig 21-7 Position Counter Reset on Index Pulse (Forward Direction)
456
Fig 21-8 Position Counter Reset on Index Pulse (Reverse Direction)
456
Velocity Measurement
459
Fig 21-14 Velocity Measurement Unit Timing Flow
460
Global Control Registers
460
Registers
460
Position Measurement Registers
463
Velocity Measurement Registers
465
Interrupt Registers
468
Features
472
Fig 22-1 I 2 S Mono/Stereo Audio-Out Interface Configuration
472
Inter-IC Sound (I 2 S)
472
Interface
472
Introduction
472
Fig 22-2 I 2 S 5.1 Channel Audio-Out Interface Configuration
473
Fig 22-3 Signal Lines in I S Data Format
473
Functional Description
473
Signal Lines
473
Operation Mode
474
Serial Data Standard
475
Clock Type
476
Fig 22-10 I 2 S Clock Tree
477
FIFO Allocation
478
Memory Block
478
Fig 22-12 FIFO Allocation of Mono Channel (Sample Bit = 16-Bit)
479
Fig 22-13 FIFO Allocation of Mono Channel (Sample Bit = 32-Bit)
479
Fig 22-14 FIFO Allocation of Stereo Channel (Sample Bit = 16-Bit)
480
Fig 22-15 FIFO Allocation of Stereo Channel (Sample Bit = 24-Bit)
480
Fig 22-16 FIFO Allocation of Stereo Channel (Sample Bit = 32-Bit)
481
Fig 22-17 FIFO Allocation of 5.1 Channel (Sample Bit = 16-Bit)
481
Fig 22-18 FIFO Allocation of 5.1 Channel (Sample Bit = 24-Bit)
482
Fig 22-19 FIFO Allocation of 5.1 Channel (Sample Bit = 32-Bit)
482
Registers
482
Control Register (IS_CTL)
483
Rx Page Pointer Register (IS_RX_PAGE_PTR)
484
Tx Page Pointer Register (IS_TX_PAGE_PTR)
484
Page Size and Sample Rate Setting Register (IS_SETTING)
485
Tx Interrupt Enable Register (IS_TX_MASK_INT)
485
Tx Interrupt Status Register (IS_TX_STATUS_INT)
486
Rx Interrupt Enable Register (IS_RX_MASK_INT)
487
Rx Interrupt Status Register (IS_RX_STATUS_INT)
488
Rx Page Own Bit Register (Is_Rx_Page_Ownx)
489
Tx Page Own Bit Register (Is_Tx_Page_Ownx)
489
Version ID (IS_VERSION_ID)
489
Abbreviations
490
Revision History
494
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