Mcr - Realtek Ameba-D RTL872 D Series User Manual

6 BREAK_CTRL
5 STICK_PARITY
4 EVEN_PARITY_SEL
3 PARITY_EN
2 STB
1 RSVD
0 WLS0

14.2.4 MCR


Name: Modem Control Register

Size: 32 bits

Address offset: 0x0010

Read/write access: read/write
31 30
RSVD
Bit Name
31:6 RSVD
5 AUTOFLOW_EN
4 LOOPBACK_EN
3 OUT2
2 OUT1
1 RTS
0 DTR
User Manual

R/W 0 Break Control bit


R/W 0 Stick Parity bit.


R/W 0 Even Parity select


R/W 0 Parity Enable


R/W 0 This is bit specifies the number of Stop bits transmitted and received in each
serial character.


Note: The receiver always checks the first stop bit only.
N/A - Reserved
R/W 1 Word length selection


... 7 6
Access Reset Description
N/A - Reserved
R/W 0 Auto Flow Enable (AFE)
This bit enables auto flow control.
R/W 0 Loopback mode

0: Normal operation

1: Loopback mode
R/W 0 This bit controls the output 2 (OUT2_) signal, which is an auxiliary user-designated output.
Bit 3 affects the OUT2_ in a manner identical to that described below for bit 0.
In loopback mode, connected to Data Carrier Detect (DCD)
R/W 0 This bit controls the Output 1 (OUT1_) signal, which is an auxiliary user-designated output.
Bit 2 affects the OUT1_ in a manner identical to that described below for bit 0.
In loopback mode, connected to Ring Indicator (RI) signal input
R/W 0 Request to Send (RTS) signal control

0: RTS is logic 1

1: RTS is logic 0
This bit controls the RTS_ output. Bit 1 affects the RTS_ output in a manner identical to that
described below for bit 0.
R/W 0 Data Terminal Ready (DTR) signal control
All information provided in this document is subject to legal disclaimers.
THR/RBR doesn't care the value of DLAB.
0: Break is disabled.
1: The serial out is forced into logic '0' (break state).
If eps bit is 1, parity bit of character shall be 0.
If eps bit is 0, parity bit of character shall be 1.
0: Odd number of logic '1' is transmitted and checked in each word (data
and parity combined). In other words, if the data has an even number of '1'
in it, then the parity bit is '1'.
1: Even number of logic '1' is transmitted in each word.
0: No parity
1: Parity bit is generated on each outgoing character and is checked on each
incoming one
0: 1 stop bit
1: 2 stop bits
0: Data is 7 bits word length.
1: Data is 8 bits word length.
5 4
AUTOFLOW_EN LOOPBACK_EN
R/W R/W
288
Ameba-D User Manual
3 2 1
OUT2 OUT1 RTS
R/W R/W R/W
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0
DTR
R/W