Realtek Ameba-D RTL872 D Series User Manual page 111

The DMAC channel FIFO has four bytes in it that must be flushed to the destination. The DMAC switches into a "FIFO flush mode," where the
block transfer to the destination is completed by changing the AHB transfer width to the destination to be equal to that of the
CTLx.SRC_TR_WIDTH; that is, byte AHB transfers in this example. Thus the last single transaction in the destination block is made up of a burst
of length 4 and CTLx.SRC_TR_WIDTH width.
When the DMAC is in FIFO flush mode, the address on haddr is incremented by the value of hsize on the bus; that is, CTLx.SRC_TR_WIDTH, and
not CTLx.DST_TR_WIDTH. In cases where the DARx is selected to be contiguous between blocks, the DARx will need re-alignment at the start of
the next block, since it is aligned to CTLx.SRC_TR_WIDTH and not CTLx.DST_TR_WIDTH at the end of the previous block. This is handled by
hardware.
In general, channel FIFO flushing to the destination occurs if all three of the following are true:

DMAC or the Source peripheral are flow control peripherals

CTLx.DST_TR_WIDTH > CTLx.SRC_TR_WIDTH

Flow control device:

If DMAC is flow controller:
blk_size_bytes_dma/dst_single_size_bytes != integer

If source is flow controller:
blk_size_bytes_src/dst_single_size_bytes != integer
Note: When not in FIFO flush mode, a single transaction is mapped to a single AHB transfer. However, in FIFO flush mode, a single transaction
is mapped to multiple AHB transfers of CTLx.SRC_TR_WIDTH width. The cumulative total of data transferred to the destination in FIFO flush
mode is less than dst_single_size_bytes.
In the above example, a burst request is not generated in the Single Transaction Region. If a burst request were generated at time t1 in Fig 9-
27, then the burst transaction would proceed until there was not enough data left in the destination block to form a single data item of
CTLx.DST_TR_WIDTH width. The burst transaction would then be early-terminated. In this example, only one data item of the four requested
(decoded value of DEST_MIZE = 4) would be transferred to the destination in the burst transaction. This is referred to as an Early-Terminated
Burst Transaction. If a burst request were generated at time t2 in Fig 9-27, then the destination block would be completed (four byte transfers
to the destination to flush the DMAC channel FIFO) and this burst request would again be early-terminated at the end of the destination block.
Observation: If the source transfer width – CTLx.SRC_TR_WIDTH in the channel control register (CTLx) – is less than the destination transfer
width (CTLx.DST_TR_WIDTH), then the FIFO may need to be flushed at the end of the block transfer. This is done by setting the AHB transfer
width of the last few AHB transfers of the block to the destination so that it is equal to CTLx.SRC_TR_WIDTH and not the programmed
CTLx.DST_TR_WIDTH.
9.2.8.1.6 Example 6
Scenario: In all examples presented so far, none of the bursts have been early-terminated by the AHB system arbiter. Referring to Example 1,
the AHB transfers on the source and destination side look somewhat symmetric. In the examples presented so far, where the bursts are not
early-terminated by the AHB system arbiter, the traffic profile on the AHB bus would be the same, regardless of the value of CFGx.FIFO_MODE.
This example, however, considers the effect of CFGx.FIFO_MODE.
CFGx.FIFO_MODE: Determines how much space or data needs to be available in the FIFO before a burst transaction request is serviced. 0 =
Space/data available for single AHB transfer of the specified transfer width. 1 = Data available is greater than or equal to half the FIFO depth for
destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst
transaction request or at the end of a block transfer.
Table 9-8 lists the parameters used in this example.
Parameter
CTLx.TT_FC = 3'b011
CTLx.BLOCK_TS = 32
CTLx.SRC_TR_WIDTH = 3'b010
CTLx.DST_TR_WIDTH = 3'b010
CTLx.SRC_MSIZE = 3'b010
CTLx.DEST_MSIZE = 3'b001
User Manual
Table 9-8 Parameters in transfer operation – Example 6
Description
Peripheral-to-peripheral transfer with DMAC as flow controller
–
32 bits
32 bits
Decode value = 8
Decode value = 4
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Direct Memory Access Controller (DMAC)
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