Realtek Ameba-D RTL872 D Series User Manual page 126

9.2.11.1 Locked DMA Transfers
It is possible to program the DMAC for:

Bus locking – Asserts the AHB hlock signal.

Channel locking – Locks the arbitration for the AHB master interface, which grants ownership of the master bus interface to one of the
requesting channel state machines (source or destination).
Bus and channel locking can proceed for the duration of a DMA transfer, a block transfer, or a single or burst transaction.
9.2.11.1.1 Bus Locking
If the LOCK_B bit in the channel configuration register (CFGx) is set, then the AHB hlock signal is asserted for the duration specified in the
LOCK_B_L field.
9.2.11.1.2 Channel Locking
If the LOCK_CH field is set, then the arbitration for the master bus interface is exclusively reserved for the source and destination peripherals of
that channel for the duration specified in the LOCK_CH_L field.
If bus locking is activated for a certain duration, then it follows that the channel is also automatically locked for that duration. Three cases arise:

CFGx.LOCK_B = 0 – Programmed values of CFGx.LOCK_CH and CFGx.LOCK_CH_L are used.

CFGx.LOCK_B = 1 and CFGx.LOCK_CH = 0 – DMA transfer proceeds as if CFGx.LOCK_CH = 1 and CFGx.LOCK_CH_L = CFGx.LOCK_B_L. The
programmed values of CFGx.LOCK_CH and CFGx.LOCK_CH_L are ignored.

CFGx.LOCK_B = 1 and CFGx.LOCK_CH = 1 – Two cases arise:

CFGx.LOCK_B_L <= CFGx.LOCK_CH_L – In this case, the DMA transfer proceeds as if CFGx.LOCK_CH_L = CFGx. LOCK_B_L and the
programmed value of CFGx.LOCK_CH_L is ignored. Thus, if bus locking is enabled over the DMA transfer level, then channel locking
is enabled over the DMA transfer level, regardless of the programmed value of CFGx.LOCK_CH_L

CFGx.LOCK_B_L > CFGx.LOCK_CH_L – The programmed value of CFGx.LOCK_CH_L is used. Thus, if bus locking is enabled over the
DMA block transfer level and channel locking is enabled over the DMA transfer level, then channel locking is performed over the
DMA transfer level.
9.2.11.1.3 Locking Levels
If locking is enabled for a channel, then locking of the AHB master bus interface at a programmed locking transfer level is activated when the
channel is first granted the AHB master bus interface at the start of that locking transfer level. It continues until the locking transfer level has
completed; that is, if channel 0 has enabled channel level locking at the block transfer level, then this channel locks the master bus interface
when it is first granted the master bus interface at the start of the block transfer, and continues to lock the master bus interface until the block
transfer has completed.
Source and destination block transfers occur successively in time, and a new source block cannot commence until the previous destination block
has completed. When both source and destination are on the same AHB layer, then block level locking is terminated on completion of the block
to the destination. If they are on separate layers, then block-level locking is terminated on completion of the block on that layer—when the
source block on the source AHB layer completes, and when the destination block on the destination AHB layer completes. The same is true for
DMA transfer-level locking.
Transaction-level locking is different due to the fact that source and destination transactions occur independently in time, and the number of
source and destination transactions in a DMA block or DMA transfer do not have to match. When the source and destination are on the same
AHB layer, then transaction-level locking is cleared at the end of a source or destination transaction only if the opposing peripheral is not
currently in the middle of a transaction.
For example, if locking is enabled at the transaction level and an end-of-source transaction is signaled, then this disables locking only if one of
the following is true:

The destination is on a different AHB layer

The destination is on the same AHB layer, but the channel is not currently in the middle of a transaction to the destination peripheral.
The same rules apply when an end-of-destination transaction is signalled.
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Ameba-D User Manual
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