Realtek Ameba-D RTL872 D Series User Manual page 82

GPIO_PWIDTH_D–1:0 External Port D
8.3.3.25 gpio_ls_sync

Name: Synchronization level

Size:1 bit

Address offset: 0x60

Read/write access: read/write
Bit Name
31:1 Reserved
0 Synchronization level
8.3.3.26 gpio_id_code

Name: GPIO ID code

Size: GPIO_ID_PWIDTH

Address offset: 0x64

Read/write access: read
Bit Name
31: GPIO_ID_PWIDTH Reserved
GPIO_ID_PWIDTH–1:0 GPIO ID code
8.3.3.27 gpio_int_bothedge

Name: GPIO INT Bothedge Type

Size: GPIO_ID_PWIDTH

Address offset: 0x68

Read/write access: read/write
This register is available only if Port A is configured to generate interrupts (GPIO_PORTA_INTR = Include (1)) and interrupt detection is
configured to generate on both rising and falling edges of external input signal (GPIO_INT_BOTH_EDGE=Include (1)).
User Manual
R
Access Description
Read as zero Reserved
R/W Writing a 1 to this register results in all level-sensitive interrupts being synchronized to
pclk_intr.
0 – No synchronization to pclk_intr (default)
1 – Synchronize to pclk_intr
Reset Value: 0x0
Access
Read as zero
R
Interrupt bothedge
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When Port D is configured as Input, then reading this location reads
the values on the signal. When the data direction of Port D is set as
Output, reading this location reads the data register for Port D.
Reset Value: 0x0
Description
Reserved
This is a user-specified code that a system can read. It can be used for chip
identification, and so on.
Reset Value: GPIO_ID_NUM
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Ameba-D User Manual
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