Realtek Ameba-D RTL872 D Series User Manual page 413

6 TXUIM R/W
5 MSTIM/FAEIM R/W
4 RXFIM R/W
3 RXOIM R/W
2 RXUIM R/W
1 TXOIM R/W
0 TXEIM R/W
19.3.2.12 ISR

Name: Interrupt Status Register

Size:

6 bits: when SSI_IS_MASTER = 1

8 bits: when SSI_IS_MASTER = 0

Address offset: 0x30

Read/write access: read
This register reports the status of the SPI interrupts after they have been masked.
31 30
7 6
SSRIS TXUIS
R R
Bit Name Access
31:8 RSVD N/A
7 SSRIS R
6 TXUIS R
User Manual
0 – ssi_ssr_intr is masked
1 – ssi_ssr_intr is not masked
1 Transmit FIFO Underflow Interrupt Mask. This bit field is present only if the SPI is configured
as a serial-slave device.
0 – ssi_txu_intr is masked
1 – ssi_txu_intr is not masked
1 When SPI is configured as serial-master, this bit field is present as Multi-Master Contention
Interrupt Mask.
0 – ssi_mst_intr interrupt is masked
1 – ssi_mst_intr interrupt is not masked
When SPI is configured as serial-slave, this bit field is present as Frame Alignment Interrupt
Mask.
0 – ssi_fae_intr interrupt is masked
1 – ssi_fae_intr interrupt is not masked
1 Receive FIFO Full Interrupt Mask.
0 – ssi_rxf_intr interrupt is masked
1 – ssi_rxf_intr interrupt is not masked
1 Receive FIFO Overflow Interrupt Mask.
0 – ssi_rxo_intr interrupt is masked
1 – ssi_rxo_intr interrupt is not masked
1 Receive FIFO Underflow Interrupt Mask.
0 – ssi_rxu_intr interrupt is masked
1 – ssi_rxu_intr interrupt is not masked
1 Transmit FIFO Overflow Interrupt Mask.
0 – ssi_txo_intr interrupt is masked
1 – ssi_txo_intr interrupt is not masked
1 Transmit FIFO Empty Interrupt Mask.
0 – ssi_txe_intr interrupt is masked
1 – ssi_txe_intr interrupt is not masked
29
5 4
MSTIS/FAEIS RXFIS
R R
Reset Description
- Reserved
0 SS_N Rising Edge Detect Interrupt Status. This bit field is present only if the SPI is configured as a
serial-slave device.
0 – ssi_ssr_intr interrupt is not active after masking
1 – ssi_ssr_intr interrupt is active after masking
0 Transmit FIFO Under Flow Interrupt Status. This bit field is present only if the SPI is configured as
a serial-slave device.
0 – ssi_txu_intr interrupt is not active after masking
All information provided in this document is subject to legal disclaimers.
... 10
RSVD
3 2
RXOIS RXUIS
R R
413
Serial Peripheral Interface (SPI)
9 8
1 0
TXOIS TXEIS
R R
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