Realtek Ameba-D RTL872 D Series User Manual page 188

i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by
programming the TT_FC of the CTLx register. Table 9-17 lists the decoding for this field.
ii. Set up the transfer characteristics, such as:

Transfer width for the source in the SRC_TR_WIDTH field; Table 9-16 lists the decoding for this field.

Transfer width for the destination in the DST_TR_WIDTH field; Table 9-16 lists the decoding for this field.

Source master layer in the SMS field where the source resides.

Destination master layer in the DMS field where the destination resides.

Incrementing/decrementing or fixed address for the source in the SINC field.

Incrementing/decrementing or fixed address for the destination in the DINC field.
e) If gather is enabled (DMAH_CHx_SRC_GAT_EN = True and CTLx.SRC_GATHER_EN is enabled), program the SGRx register for channel
x.
f) If scatter is enabled (DMAH_CHx_DST_SCA_EN = True and CTLx.DST_SCATTER_EN), program the DSRx register for channel x.
g) Write the channel configuration information into the CFGx register for channel x.
i. Designate the handshaking interface type (hardware or software) for the source and destination peripherals; this is not
required for memory.
This step requires programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a 0 activates the hardware
handshaking interface to handle source/destination requests for the specific channel. Writing a 1 activates the software
handshaking interface to handle source/destination requests.
ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign the handshaking interface
to the source and destination peripheral. This requires programming the SRC_PER and DEST_PER bits, respectively.
(4) After the DMAC channel has been programmed, enable the channel by writing a 1 to the ChEnReg.CH_EN bit. Ensure that bit 0 of the
DmaCfgReg register is enabled.
(5) Source and destination request single and burst DMAC transactions to transfer the block of data (assuming non-memory peripherals). The
DMAC acknowledges on completion of each burst/single transaction and carries out the block transfer.
(6) When the block transfer has completed, the DMAC reloads the SARx register; the DARx register remains unchanged. Hardware sets the
block-complete interrupt. The DMAC then samples the row number, as shown in Table 9-19. If the DMAC is in Row 1, then the DMA
transfer has completed. Hardware sets the transfer complete interrupt and disables the channel. You can either respond to the Block
Complete or Transfer Complete interrupts, or poll for the transfer complete raw interrupt status register (RawTfr[n], n = channel number)
until it is set by hardware, in order to detect when the transfer is complete. Note that if this polling is used, software must ensure that
the transfer complete interrupt is cleared by writing to the Interrupt Clear register, ClearTfr[n], before the channel is enabled. If the
DMAC is not in Row 1, the next step is performed.
(7) The DMA transfer proceeds as follows:
a) If interrupts are enabled (CTLxx.INT_EN = 1) and the block-complete interrupt is unmasked (MaskBlock[x] = 1'b1, where x is the
channel number), hardware sets the block-complete interrupt when the block transfer has completed. It then stalls until the block-
complete interrupt is cleared by software. If the next block is to be the last block in the DMA transfer, then the block-complete ISR
(interrupt service routine) should clear the source reload bit, CFGx.RELOAD_SRC. This puts the DMAC into Row 1, as shown in Table
9-19. If the next block is not the last block in the DMA transfer, then the source reload bit should remain enabled to keep the DMAC
in Row 3, as shown in Table 9-19.
b) If interrupts are disabled (CTLx.INT_EN = 0) or the block-complete interrupt is masked (MaskBlock[x] = 1'b0, where x is the channel
number), then hardware does not stall until it detects a write to the block-complete interrupt clear register; instead, it starts the
next block transfer immediately. In this case, software must clear the source reload bit, CFGx.RELOAD_SRC, to put the device into
Row 1 of Table 9-19 before the last block of the DMA transfer has completed.
The transfer is similar to that shown in Fig 9-57.
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