Realtek Ameba-D RTL872 D Series User Manual page 282

Bit Name
31:2 RSVD
1 IC_SLEEP_CLK_GATED
0 IC_SLEEP
13.3.2.45 IC_CLR_ADDR_MATCH

Name: Clear Slave Mode Address Match Interrupt Register

Size: 32 bits

Address offset: 0xE4

Read/write access: read-only
31 30
Bit Name
31:1 RSVD
0 IC_CLR_ADDR_MATCH
13.3.2.46 IC_CLR_DMA_DONE

Name: Clear DMA_DONE Interrupt Register

Size: 32 bits

Address offset: 0xE8

Read/write access: read-only
31 30
Bit Name
31:1 RSVD
0 IC_CLR_DMA_DONE
13.3.2.47 IC_FILTER

2
Name: I C Filter Register

Size: 32 bits

Address offset: 0xEC

Read/write access: read/write
31 30 ...
RSVD
Bit Name
31:9 RSVD
User Manual
RSVD
Access Reset Description
N/A - Reserved
2
R 0x0 I C clock has been gated.
R/W 0x0 Clock-gated I

1: I

0: I
enable and reset synchronized register procedure is done.
29 ...
RSVD
Access Reset Description
N/A - Reserved
R 0x0 Read this register to clear the slave mode address match interrupt (bit 12) of
IC_RAW_INTR_STAT register.
29 ...
RSVD
Access Reset Description
N/A - Reserved
R 0x0 Read this register to clear the DMA_DONE interrupt (bit 15) of IC_RAW_INTR_STAT
register.
10 9 8
IC_DIG_FLTR_SEL
R/W
Access Reset Description
N/A - Reserved
All information provided in this document is subject to legal disclaimers.
2 C clock domain for address matching interrupts wake up.
2 C clock has been gated
2 C clock control, write 1 controller would gate I
3
3
7 6 5
RSVD
282
Ameba-D User Manual
IC_SLEEP_CLK_GATED
R
2 C clock until I
2 1
IC_CLR_ADDR_MATCH
2 1
4 3 2
IC_DIG_FLTR_DEG
R/W
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IC_SLEEP
R/W
2 C slave is
0
R
0
IC_CLR_DMA_DONE
R
1 0