Realtek Ameba-D RTL872 D Series User Manual page 190

(1) Read the Channel Enable register in order to choose a free (disabled) channel.
(2) Set up the linked list in memory. Write the control information in the LLI.CTLx register location of the block descriptor for each LLI in
memory (see Fig 9-45) for channel x. For example, in the register, you can program the following:
a) Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming
the TT_FC of the CTLx register. Table 9-17 lists the decoding for this field.
b) Set up the transfer characteristics, such as:
i. Transfer width for the source in the SRC_TR_WIDTH field. Table 9-16 lists the decoding for this field.
ii. Transfer width for the destination in the DST_TR_WIDTH field. Table 9-16 lists the decoding for this field.
iii. Source master layer in the SMS field where the source resides.
iv. Destination master layer in the DMS field where the destination resides.
v. Incrementing/decrementing or fixed address for the source in the SINC field.
vi. Incrementing/decrementing or fixed address for the destination in the DINC field.
(3) Write the starting source address in the DARx register for channel x.
Note: The values in the LLI.DARx register locations of each of the Linked List Items (LLIs) set up in memory, although fetched during an LLI
fetch, are not used.
(4) Write the channel configuration information into the CFGx register for channel x.
a) Designate the handshaking interface type (hardware or software) for the source and destination peripherals; this is not required for
memory.
This step requires programming the HS_SEL_SRC/HS_SEL_DST bits. Writing a 0 activates the hardware handshaking interface to
handle source/destination requests for the specific channel. Writing a 1 activates the software handshaking interface to handle
source/destination requests.
b) If the hardware handshaking interface is activated for the source or destination peripheral, assign the handshaking interface to the
source and destination peripheral. This requires programming the SRC_PER and DEST_PER bits, respectively.
(5) Ensure that the LLI.CTLx register locations of all LLI (except the last) are set as shown in Row 8 of Table 9-19, while the LLI.CTLx register of
the last Linked List Item must be set as described in Row 1 or Row 5 of Table 9-19. Fig 9-45 shows a Linked List example with two list
items.
(6) Ensure that the LLI.LLPx register locations of all LLI entries in memory (except the last) are non-zero and point to the next Linked List Item.
(7) Ensure that the LLI.SARx register locations of all LLI entries in memory point to the start destination block address preceding that LLI fetch.
(8) If DMAH_CHx_CTL_WB_EN = True, ensure that the LLI.CTLx.DONE field of the LLI.CTLx register locations of all LLIs in memory are cleared.
(9) If source status fetching is enabled (DMAH_CHx_CTL_WB_EN = True, DMAH_CHx_STAT_SRC = True, and CFGx.SS_UPD_EN is enabled),
program the SSTATARx register so that the source status information can be fetched from the location pointed to by the SSTATARx. For
conditions under which the source status information is fetched from system memory, refer to the Write Back column of Table 9-19 .
(10) If destination status fetching is enabled (DMAH_CHx_CTL_WB_EN = True, DMAH_CHx_STAT_DST = True, and CFGx.DS_UPD_EN is
enabled), program the DSTATARx register so that the destination status information can be fetched from the location pointed to by the
DSTATARx register. For conditions under which the destination status information is fetched from system memory, refer to the Write
Back column of Table 9-19.
(11) If gather is enabled (DMAH_CHx_SRC_GAT_EN = True and CTLx.SRC_GATHER_EN is enabled), program the SGRx register for channel x.
(12) If scatter is enabled (DMAH_CHx_DST_SCA_EN = True and CTLx.DST_SCATTER_EN is enabled) program the DSRx register for channel x.
(13) Clear any pending interrupts on the channel from the previous DMA transfer by writing to the Interrupt Clear registers: ClearTfr,
ClearBlock, ClearSrcTran, ClearDstTran, and ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that all
interrupts have been cleared.
(14) Program the CTLx and CFGx registers according to Row 8, as shown in Table 9-19.
(15) Program the LLPx register with LLPx(0), the pointer to the first linked list item.
(16) Finally, enable the channel by writing a 1 to the ChEnReg.CH_EN bit; the transfer is performed. Ensure that bit 0 of the DmaCfgReg
register is enabled.
(17) The DMAC fetches the first LLI from the location pointed to by LLPx(0).
Note: The LLI.SARx, LLI.DARx, LLI.LLPx, and LLI.CTLx registers are fetched. The LLI.DARx register – although fetched – is not used. The
DARx register in the DMAC remains unchanged.
(18) Source and destination request single and burst DMAC transactions in order to transfer the block of data (assuming non-memory
peripheral). The DMAC acknowledges at the completion of every transaction (burst and single) in the block and carries out the block
transfer.
(19) Once the block of data is transferred, the source status information is fetched from the location pointed to by the SSTATARx register and
stored in the SSTATx register if DMAH_CHx_CTL_WB_EN = True, DMAH_CHx_STAT_SRC = True, and CFGx.SS_UPD_EN is enabled. For
conditions under which the source status information is fetched from system memory, refer to the Write Back column of Table 9-19.
The destination status information is fetched from the location pointed to by the DSTATARx register and stored in the DSTATx register if
DMAH_CHx_CTL_WB_EN = True, DMAH_CHx_STAT_DST = True, and CFGx.DS_UPD_EN is enabled. For conditions under which the
destination status information is fetched from system memory, refer to the Write Back column of Table 9-19.
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Ameba-D User Manual
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