Realtek Ameba-D RTL872 D Series User Manual page 447


Address offset: 0x0060

Read/write access: read/write
31 30
15 14
RSVD
7 6
MCUSYPL
RSVD
R/W
Bit Name
31:16 TEDELAY
15:13 RSVD
12 MCU_IO_MODE_RUN
11 MCU_IO_MODE_EN
10:9 MCU_SYNC_MODE
8 MCUIFUPDATE
7 RSVD
6 MCUSYPL
5 TEPL
4 DATAPL
3 RDPL
2 WRPL
1 RSPL
User Manual
29 28
13 12
MCU_IO_MODE_RUN
RO
5 4
TEPL DATAPL
R/W R/W
Access Reset Description
R/W 0 The delay interval -5. This interval is from detected TE signal to starting frame
transfer. Unit: WR pulse width.
The maximum value is 65535.
The real delay interval is TEDELAY + 4 or TEDELAY + 5.
N/A 0 Reserved
RO 0 MCU I/F I/O mode run

0: DMA mode run

1: I/O mode run
R/W 0 MCU I/F I/O mode enable

0: Disable I/O mode and open DMA mode after I/O mode FIFO empty.

1: Enable I/O mode after current frame refresh.
Poll MCU_IO_MODE_RUN after updating this bit.

R/W 1 00: Synchronized with the internal clock

01: Synchronized with VSYNC input

10: Tearing effect line on (Mode1, VSYNC)

Others: Reserved
R/W1S 0 Force Hardware to update MCU I/F Timing shadow register at specific timing. CPU
writes 1 to force Hardware updating. After Hardware updating finished, this bit is
cleared. Software can't write related shadow registers when MCUIFUPDATE is still
active.
When the LCDC is running, if the following values related with MCU I/F mode are
modified dynamically, only writing 1 to this bit can the newer value be used by
hardware after the current frame refresh done.

The TEDELAY field in the LCDC_MCU_CFG register

The MCUVSW, MCUVSPD fields in the

The WRPULW, RDACTW, RDINACTW fields in the
register
N/A 0 Reserved
R/W 0 The MCU VSYNC pulse polarity

0: Low level for active pulse

1: High level for active pulse
R/W 1 The TE pulse polarity.

0: Low level for active pulse

1: High level for active pulse
R/W 0 The Data pulse polarity.

0: Normal

1: Inverted
R/W 0 The RD pulse polarity.

0: Data fetched at rising edge

1: Data fetched at falling edge
R/W 0 The WR pulse polarity.

0: Data fetched at rising edge

1: Data fetched at falling edge
R/W 0 The RS pulse polarity.
All information provided in this document is subject to legal disclaimers.
... 19 18
TEDELAY
R/W
11 10
MCU_IO_MODE_EN
R/W
3
RDPL WRPL
R/W R/W
447
Liquid Crystal Display Controller (LCDC)
17
9
MCU_SYNC_MODE MCUIFUPDATE
R/W
2 1
RSPL
R/W
LCDC_MCU_VSYNC_CFG register
LCDC_MCU_TIMING_CFG
© REALTEK 2019. All rights reserved.
16
8
R/W1S
0
CSPL
R/W