Realtek Ameba-D RTL872 D Series User Manual page 15

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Fig 17-2 Cap-less mode connection with headphone jack............................................................................................................... 333

Fig 17-3 Differential mode connection with headphone jack .......................................................................................................... 334

Fig 17-4 Single-end mode connection with headphone jack ........................................................................................................... 334

Fig 17-5 Line-in mode connection .................................................................................................................................................... 335

Fig 17-6 Analog MIC single-end mode connection .......................................................................................................................... 335

Fig 17-7 Analog MIC differential mode connection ......................................................................................................................... 335

Fig 17-8 Digital MIC mono mode connection .................................................................................................................................. 336

Fig 17-9 Digital MIC stereo mode connection .................................................................................................................................. 336

Fig 17-10 Mono PDM format ........................................................................................................................................................... 336

Fig 17-11 Stereo PDM format .......................................................................................................................................................... 337

Fig 17-12 I

S acting as PDM .............................................................................................................................................................. 337

Fig 18-1 Ameba-D ACC + AC architecture ........................................................................................................................................ 381

Fig 18-2 ACC block diagram ............................................................................................................................................................. 382

Fig 18-3 I

S audio data format ......................................................................................................................................................... 385

Fig 18-4 Left-Justified data format ................................................................................................................................................... 386

Fig 18-5 PCM mode B data format ................................................................................................................................................... 386

Fig 18-6 PCM mode B-N data format ............................................................................................................................................... 386

Fig 18-7 PCM mode A data format .................................................................................................................................................. 386

Fig 18-8 PCM mode A-N data format ............................................................................................................................................... 387

Fig 18-9 SI write timing .................................................................................................................................................................... 387

Fig 18-10 SI read timing ................................................................................................................................................................... 388

Fig 18-11 ACC clock architecture ..................................................................................................................................................... 388

Fig 19-1 SPI block diagram ............................................................................................................................................................... 395

Fig 19-2 SPI Serial Format (SCPH = 0) ............................................................................................................................................... 397

Fig 19-3 SPI Serial Format Continuous Transfers (SCPH = 0 and SS toggling) .................................................................................. 397

Fig 19-4 SPI Serial Format Continuous Transfers (SCPH = 0 and SS not-toggling) ........................................................................... 397

Fig 19-5 SPI Serial Format (SCPH = 1) ............................................................................................................................................... 398

Fig 19-6 SPI Serial Format Continuous Transfers (SCPH = 1)............................................................................................................ 398

Fig 19-7 Maximum sclk_out/ssi_clk Ratio ........................................................................................................................................ 399

Fig 19-8 SPI Configured as master device ........................................................................................................................................ 401

Fig 19-9 Effects of round trip routing delays on sclk_out signal ...................................................................................................... 401

Fig 20-1 MCU I/F + LCM with GRAM ................................................................................................................................................ 422

Fig 20-2 RGB I/F + LCM without GRAM ............................................................................................................................................ 422

Fig 20-3 LCDC block diagram ............................................................................................................................................................ 422

Fig 20-4 Two data paths ................................................................................................................................................................... 423

Fig 20-5 MCU I/O mode application scenario .................................................................................................................................. 423

Fig 20-6 DMA mode application scenario ........................................................................................................................................ 424

Fig 20-7 MCU interface .................................................................................................................................................................... 424

Fig 20-8 MCU I/F command setting timing parameters .................................................................................................................. 425

Fig 20-9 MCU I/F data writing timing parameters ........................................................................................................................... 425

Fig 20-10 MCU I/F read command timing parameters .................................................................................................................... 425

Fig 20-11 MCU VSYNC mode timing ................................................................................................................................................ 426

Fig 20-12 MCU TE mode timing ....................................................................................................................................................... 426

Fig 20-13 MCU TE mode frame synchronization ............................................................................................................................. 426

Fig 20-14 8080 I/F 8-bit output ........................................................................................................................................................ 427

Fig 20-15 8080 I/F 16-bit output ...................................................................................................................................................... 427

Fig 20-16 RGB interface ................................................................................................................................................................... 428

Fig 20-17 RGB timing........................................................................................................................................................................ 428

Fig 20-18 RGB DE mode timing ........................................................................................................................................................ 429

Fig 20-19 RGB I/F 6-bit output ......................................................................................................................................................... 429

Fig 20-20 RGB I/F 16-bit output ....................................................................................................................................................... 430

Fig 20-21 LED interface .................................................................................................................................................................... 431

Fig 20-22 LED control timing ............................................................................................................................................................ 432

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