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SP – 4
SP – 3
SP – 2
SP – 1
SP (R7)
Stack
Prior to start of interrupt
exception handling
Notation
PC
:
Upper 8 bits of program counter (PC)
H
PC
:
Lower 8 bits of program counter (PC)
L
CCR:
Condition code register
SP:
Stack pointer
Notes:
* Ignored on return from interrupt.
1.
PC shows the address of the first instruction to be executed upon
return from the interrupt.
2.
Saving and restoring of register contents must always be done
in word size, and must start from an even-numbered address.
Figure 3-4. Stack State after Completion of Interrupt Exception Handling
3.3
Reset State
# $
When the
pin goes to low level, all processing stops and the system goes to reset state. The
I bit of the condition code register (CCR) is set, masking all interrupts.
# $
After the
pin is changed externally from low to high level, reset exception handling starts at
the point when the reset conditions are met. For details on reset conditions refer to the applicable
hardware manual.
3.4
Power-Down State
In power-down state the CPU operation is stopped, reducing power consumption. For details see
the applicable hardware manual.
SP (R7)
SP + 1
SP + 2
SP + 3
SP + 4
After completion of interrupt
Contents
exception handling
saved to stack
CCR
CCR*
PC
H
PC
L
Even-numbered
address
149
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