Oscillators/Clocks; Usb-Uart Bridge (Serial Port) - Xilinx Arty A7 Reference Manual

22.8.2018
Vivado IPI based designs can access the PHY using either the AXI EthernetLite IP core, the AXI 1G/2.5G Ethernet Subsystem IP core,
or the Tri Mode Ethernet MAC IP core. A 25 MHz () clock needs to be generated for the X1 pin of the external PHY, labeled
ETH_REF_CLK in the Arty A7 schematic. To learn how to properly use the Ethernet PHY in a Microblaze design on the Arty, refer to
the Getting Started with Microblaze Servers tutorial on the Arty A7 Resource Center.
For further information on the Ethernet PHY, refer to the DP83848J data sheet.
(https://reference.digilentinc.com/_detail/arty/arty_eth.png?id=reference%3Aprogrammable-logic%3Aarty-a7%3Areference-manual)
Figure 6.1 Arty A7 Ethernet

7 Oscillators/Clocks

The Arty A7 includes a single 100 MHz () crystal oscillator connected to pin E3 (E3 is a MRCC input on bank 35). The input clock can
drive MMCMs or PLLs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a
design. Some rules restrict which MMCMs and PLLs may be driven by the 100 MHz () input clock. For a full description of these rules
and of the capabilities of the Artix-7 clocking resources, refer to the "7 Series FPGAs Clocking Resources User Guide" available from
Xilinx.
Xilinx offers the Clocking Wizard IP core to help users generate the different clocks required for a specific design. This wizard will
properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user. The
wizard will then output an easy-to-use wrapper component around these clocking resources that can be inserted into the user's design.
The clocking wizard can be accessed from within the Project Navigator or Core Generator tools.

8 USB-UART Bridge (Serial Port)

The Arty A7 includes an FTDI FT2232HQ USB-UART bridge (attached to connector J10) that allows you use PC applications to
communicate with the board using standard Windows COM port commands. Free USB-COM port drivers, available from
www.ftdichip.com
(http://www.ftdichip.com)
data. Serial port data is exchanged with the FPGA using a two-wire serial port (TXD/RXD). After the drivers are installed, I/O
commands can be used from the PC directed to the COM port to produce serial data traffic on the A9 and D10 FPGA pins.
Two on-board status LEDs provide visual feedback on traffic flowing through the port: the transmit LED () (LD10) and the receive
LED () (LD9). Signal names that imply direction are from the point-of-view of the DTE (Data Terminal Equipment), in this case the PC.
The FT2232HQ is also used as the controller for the Digilent USB-JTAG circuitry, but the USB-UART and USB-JTAG functions
behave entirely independent of one another. Programmers interested in using the UART functionality of the FT2232 within their design
do not need to worry about the JTAG circuitry interfering with the UART data transfers, and vice-versa. The combination of these two
features into a single device allows the Arty A7 to be programmed, communicated with via UART, and powered from a computer
attached with a single Micro USB cable.
https://reference.digilentinc.com/reference/programmable-logic/arty-a7/reference-manual
Arty A7 Reference Manual [Reference.Digilentinc]
under the "Virtual Com Port" or VCP heading, convert USB packets to UART/serial port
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