Features; Figure 24. Gpio Pin Routing Topology; Table 13. Gpio Pin Routing Guidelines - Intel Quark D2000 Design Manual

Figure 24. GPIO Pin Routing Topology

Table 13. GPIO Pin Routing Guidelines

GPIO (MV to GPIO
Header/Device)
Transmission Line Segment
Routing Layer
(Microstrip/Stripline)
Characteristic Impedance
Trace Width (w)
Trace Spacing (S): Between
SPI signals
Trace Spacing (S2):
Between SPI signals and
other signals
Trace Length
Trace Total Length
NOTE:
1.
2.
3.
9.2

Features

The following is a list of the GPIO controller features:
 26 independently configurable GPIOs
 Separate data register bit and data direction control bit for each GPIO
Intel® Quark™ Microcontroller D2000
Platform Design Guide
36
50Ω + 10% (MS)
50Ω + 10% (SL)
Meet impedance
Rs = 22 or 33Ω ideally closer to driver.
The modelled GPIO device is 30pF. GPIOs can drive higher loads at reduced lengths.
Maximum speed = 8 MHz.
BRK OUT
L1
MS/SL MS/SL
50Ω + 10% (MS)
50Ω + 10% (SL)
Meet impedance
5 mil minimum
5 mil minimum
0.5" max 9" max
Total trace length = 10" max
General Purpose I/O (GPIO)
GPIO
Main BRK IN
L2 L3
MS/SL
50Ω + 10% (MS)
50Ω + 10% (SL)
Meet impedance
2*w 5 mil minimum
3*w 5 mil minimum
0.5" max
November 2016
Document Number: 333580-002EN