Features; Table 24. Gpio Pin Routing Guidelines - Intel Quark SE Series Platform Manual

General Purpose I/O (GPIO)

Table 24. GPIO Pin Routing Guidelines

GPIO (MV to GPIO
Header/Device)
Transmission Line Segment
Routing Layer
(Microstrip/Stripline)
Characteristic Impedance
Trace Width (w)
Trace Spacing (S): Between
SPI signals
Trace Spacing (S2): Between
SPI signals and other signals
Trace Length
Trace Total Length
1.
2.
3.
9.2

Features

The following is a list of the GPIO controller features:
 32 independently configurable GPIOs

6 additional AON GPIOs
 Separate data register bit and data direction control bit for each GPIO
 Metastability registers for GPIO read data
 Interrupt mode supported for all GPIOs, configurable as follows:





 Debounce logic for interrupt sources
June 2017
Document Number: 334715-004EN
Rs = 22 or 33Ω ideally closer to driver
The modelled GPIO device is 30pF; GPIOs can drive higher loads at reduced lengths
Maximum speed = 8 MHz
Active High Level
Active Low Level
Rising Edge
Falling Edge
Both Edge
BRK OUT
L1
MS/SL
50Ω + 10% (MS) 50Ω + 10% (MS)
50Ω + 10% (SL) 50Ω + 10% (SL)
Meet impedance Meet impedance
5 mils minimum
5 mils minimum
0.5" max
Total trace length = 10" max
§
Intel® Quark™ SE Microcontroller C1000
GPIO
Main BRK IN
L2 L3
MS/SL MS/SL
50Ω + 10% (MS)
50Ω + 10% (SL)
Meet impedance
2W 5 mils minimum
3W 5 mils minimum
9" max 0.5" max
Platform Design Guide
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