Program And Data Memory Stalls - Texas Instruments TMS320C6000 Series Reference Manual

6.4.3.1 Memory Stalls
Figure 6–30. Program and Data Memory Stalls
Fetch
packet
(FP) 1 2
n
PG PS
n+1
PG
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
n+10
In the instance where multiple accesses are made to a single ported memory,
the pipeline will stall to allow the extra access to occur. This is called a memory
bank hit and is discussed in section 6.4.3.2, Memory Bank Hits .
A memory stall occurs when memory is not ready to respond to an access from
the CPU. This access occurs during the PW phase for a program memory
access and during the E3 phase for a data memory access. The memory stall
causes all of the pipeline phases to lengthen beyond a single clock cycle,
causing execution to take additional clock cycles to finish. The results of the
program execution are identical whether a stall occurs or not. Figure 6–30
illustrates this point.
3 4 5 6
PW PR DP DC
PS PW PR DP
PG PS PW PR
PG PS PW
É É É
PG PS
É É É
PG
Clock cycle
7 8 9 10
É É
E1 E2
É É
DC E1
DP Program DC
PR memory stall DP
PW PR
PS PW
PG PS
PG
Performance Considerations
11 12 13 14
E3
E2
E1
DC Data
DP memory stall
PR
PW
PS
PG
TMS320C67x Pipeline
15 16
E4 E5
E3 E4
E2 E3
E1 E2
DC E1
DP DC
PR DP
PW PR
PS PW
PG PS
PG
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