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Table 6–34. Loads in Pipeline From Example 6–2
Figure 6–32. 8-Bank Interleaved Memory With Two Memory Spaces
Memory space 0
1
0
2
16
17
18
16N
16N
+
1
16N
+
2
16N
Bank 0
Bank 1
Memory space 1
16M
16
M
+1
16M
+
2
16M
Bank 0
Bank 1
i
LDW .D1
E1
Bank 0
LDW .D2
E1
Bank 0
For devices that have more than one memory space (see Figure 6–32), an
access to bank 0 in one space does not interfere with an access to bank 0 in
another memory space, and no pipeline stall occurs.
The internal memory of the 'C67x family varies from device to device. See the
TMS320C62x/C67x Peripherals Reference Guide to determine the memory
spaces in your particular device.
3
5
4
6
19
20
21
22
16N
+
4
+
3
16N
+
5
16N
+
Bank 2
Bank 3
+
3
16M
+
4
16M
+
5
16M
+
Bank 2
Bank 3
i + 1
i + 2
E2
E3
E2
–
7
9
8
23
24
25
6
16N
+
7
16N
+
8
16N
+
9
16N
Bank 4
6
16M
+
7
16M
+
8
16M
+
9
16M
Bank 4
Performance Considerations
i + 3
i + 4
–
E4
E3
E4
11
13
10
12
26
27
28
29
+
0 1
16N
+
1 1
16N
+
12
16N
+
13
Bank 5
Bank 6
+
0 1
16M
+
1 1
16M
+
12
16M
+
13
Bank 5
Bank 6
TMS320C67x Pipeline
i + 5
E5
E5
15
14
30
31
16N
+
14
16N
+
15
Bank 7
16M
+
14
16M
+
15
Bank 7
6-59
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