Figure 6–2. Fetch Phases of the Pipeline
(a)
PG
PS
PW
(c)
Fetch
LDW
LDW
LDW
LDW
(b)
PR
LDW
SHR
SHR
LDW
SMPYH
SMPY
LDW
MVKLH
MV
LDW
MVK
ADD
CPU
Functional
units
Registers
PG
256
SMPYH
SMPYH
SADD
SADD
SMPYH
SMPY
SHL
LDW
Decode
Pipeline Operation Overview
PR
Memory
PS
PW
MV
NOP
B
MVK
B
MVK
LDW
MVK
TMS320C67x Pipeline
PG
PS
PW
PR
6-3