Load Instruction Phases; Load Execution Block Diagram - Texas Instruments TMS320C6000 Series Reference Manual

5.2.4 Load Instructions
Figure 5–14. Load Instruction Phases
Figure 5–15. Load Execution Block Diagram
Data loads require all five of the pipeline execute phases to complete their op-
erations. Figure 5–14 shows the pipeline phases the load instructions use.
PG PS PW
Figure 5–15 shows the operations occurring in the pipeline phases for a load.
In the E1 phase, the data address pointer is modified in its register. In the E2
phase, the data address is sent to data memory. In the E3 phase, a memory
read at that address is performed.
E5
E4
In the E4 stage of a load, the data is received at the CPU core boundary. Final-
ly, in the E5 phase, the data is loaded into a register. Because data is not written
to the register until E5, load instructions have four delay slots. Because pointer
results are written to the register in E1, there are no delay slots associated with
the address modification.
Pipeline Execution of Instruction Types
PR DP DC
Functional
unit
.D
E1
Register file
Data
Memory controller
Memory
E1 E2 E3 E4
4 delay slots
E2
Address
E3
TMS320C62x Pipeline
E5
5-15