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2.6.1
Addressing Mode Register (AMR)
Figure 2–4. Addressing Mode Register (AMR)
Table 2–4. Addressing Mode Register (AMR) Mode Select Field Encoding
For each of the eight registers (A4–A7, B4–B7) that can perform linear or circu-
lar addressing, the AMR specifies the addressing mode. A 2-bit field for each
register selects the address modification mode: linear (the default) or circular
mode. With circular addressing, the field also specifies which BK (block size)
field to use for a circular buffer. In addition, the buffer must be aligned on a byte
boundary equal to the block size. The mode select fields and block size fields
are shown in Figure 2–4, and the mode select field encoding is shown in
Table 2–4.
31
Reserved
R, +0
15
14
13
12
11
B7 mode
B6 mode
B5 mode
Legend: R
Readable by the MVC instruction
W
Writeable by the MVC instruction
+0
Value is zero after reset
The reserved portion of AMR is always 0. The AMR is initialized to 0 at reset.
TMS320C62x/C67x Control Register File
26
25
BK1
R, W, +0
Mode select fields
10
9
8
7
B4 mode
A7 mode
R, W, +0
Mode
Description
0 0
Linear modification
(default at reset)
0 1
Circular addressing using
the BK0 field
1 0
Circular addressing using
the BK1 field
1 1
Reserved
CPU Data Paths and Control
Block size fields
21 20
BK0
R, W, +0
6
5
4
3
2
A6 mode
A5 mode
16
1
0
A4 mode
2-9
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