Pipeline
Instruction Type
Delay Slots
Functional Unit
Latency
Example
Before instruction
A1:A0 4021 3333h
B3:B2 c004 0000h
A4 XXXX XXXXh
Double-Precision Floating-Point Compare for Less Than
Note:
No configuration bits besides those shown in the preceding table are set, ex-
cept for the NaNn and DENn bits when appropriate.
Pipeline
E1
Stage
src1_l
Read
src2_l
Written
Unit in use
.S
DP compare
1
2
CMPLTDP
.S1X
3333 3333h
8.6
0000 0000h
–2.5
E2
src1_h
src2_h
dst
.S
A1:A0,B3:B2,A4
2 cycles after instruction
A1:A0 4021 3333h
B3:B2 c004 0000h
A4 0000 0000h
TMS320C67x Floating-Point Instruction Set
CMPLTDP
4021 3333h
8.6
0000 0000h
–2.5
false
4-37
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