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LDB(U)/LDH(U)/LDW
Table 3–15. Data Types Supported by Loads
Execution
Pipeline
Instruction Type
Delay Slots
3-72
Load From Memory With a 15-Bit Constant Offset
Word and halfword addresses must be aligned on word (two LSBs are 0) and
halfword (LSB is 0) boundaries, respectively.
ld/st
Mnemonic
Field
LDB
0 1 0
LDBU
0 0 1
LDH
1 0 0
LDHU
0 0 0
LDW
1 1 0
if (cond)
mem
dst
else
nop
Note:
This instruction executes only on the B side (.D2).
Pipeline
Stage
E1
B14 / B15
Read
Written
Unit in use
.D2
Load
4
Load Data Type
Load byte
Load byte unsigned
Load halfword
Load halfword unsigned
Load word
E2
E3
Left
Shift of
SIze
Offset
8
0 bits
8
0 bits
16
1 bit
16
1 bit
32
2 bits
E4
E5
dst
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