Mcbsp Operation; Data Transfer Process Of A Mcbsp; Data Transfer Process For Word Length Of 8, 12, Or 16 Bits; Mcbsp Data Transfer Paths - Texas Instruments TMS320VC5501 Reference Manual

Data Transfer Process of a McBSP

2.1 Data Transfer Process of a McBSP
Figure 2−1. McBSP Data Transfer Paths
Á Á Á Á
RSR[1,2]
DR
Á Á Á Á
XSR[1,2]
DX Á Á Á Á
Á Á Á Á
2.1.1

Data Transfer Process for Word Length of 8, 12, or 16 Bits

2-2

McBSP Operation

Figure 2−1 shows a diagram of the McBSP data transfer paths. McBSP
receive operation is triple buffered, and transmit operation is double buffered.
The use of registers varies depending on whether the defined length of each
serial word fits in 16 bits.
Compand
Á Á Á Á Á Á Á Á Á
RBR[1,2] RBR[1,2]
Expand
Á Á Á Á Á Á Á Á Á
Compress
Á Á Á Á Á
Á Á Á Á Á
If the word length is 16 bits or smaller, only one 16-bit register is needed at each
stage of the data transfer paths. The registers DRR2, RBR2, RSR2, DXR2,
and XSR2 are not used (written, read, or shifted).
Receive data arrives on the DR pin and is shifted into receive shift register 1
(RSR1). Once a full word is received, the content of RSR1 is copied to receive
buffer register 1 (RBR1), only if RBR1 is not full with previous data. RBR1 is
then copied to data receive register 1 (DRR1), unless the previous content of
DRR1 has not been read by the CPU or the DMA controller. If the companding
feature of the McBSP is implemented, the required word length is 8 bits and
receive data is expanded into the appropriate format before being passed from
RBR1 to DRR1.
Transmit data is written by the CPU or the DMA controller to data transmit
register 1 (DXR1). If there is no previous data in transmit shift register (XSR1),
the value in DXR1 is copied to XSR1; otherwise, DXR1 is copied to XSR1 when
the last bit of the previous data is shifted out on the DX pin. If selected, the
companding module compresses 16-bit data into the appropriate 8-bit format
before passing it to XSR1. After transmit frame synchronization, the
transmitter begins shifting bits from XSR1 to the DX pin.
Á Á Á
DRR[1,2] DRR[1,2]
To CPU or DMA controller
Á Á Á
From CPU or DMA controller
DXR[1,2]
Á Á Á
Á Á Á
SPRU592E