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1.4 TMS320C62x/C67x Architecture
Figure 1–1. TMS320C62x/C67x Block Diagram
'C62x/'C67x device
DMA, EMIF
Figure 1–1 is the block diagram for the TMS320C62x/C67x DSPs. The
'C62x/C67x devices come with program memory, which, on some devices,
can be used as a program cache. The devices also have varying sizes of data
memory. Peripherals such as a direct memory access (DMA) controller,
power-down logic, and external memory interface (EMIF) usually come with
the CPU, while peripherals such as serial ports and host ports are on only
certain devices. Check the data sheet for your device to determine the specific
peripheral configurations you have.
Program cache/program memory
32-bit address
256-bit data
Power
down
Data path A
Register file A
.L1
.S1
Data cache/data memory
32-bit address
8-, 16-, 32-bit data
Program fetch
Instruction dispatch
Instruction decode
Data path B
Register file B
.D2 .M2
.M1
.D1
TMS320C62x/C67x Architecture
'C62x/C67x CPU
Control
registers
Control
logic
Test
Emulation
.S2 .L2
Interrupts
Additional
peripherals:
Timers,
serial ports,
etc.
Introduction
1-7
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