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6.1.3
Execute
Figure 6–4. Execute Phases of the Pipeline and Functional Block Diagram of the
TMS320C67x
(a)
E1
E2
E3
(b)
Execute
SADD
B
.L1
.S1
15
14
13
12 11
10
9
Register file A
32
Data address 1
The execute portion of the floating-point pipeline is subdivided into ten phases
(E1–E10), as compared to the fixed-point pipeline's five phases. Different
types of instructions require different numbers of these phases to complete
their execution. These phases of the pipeline play an important role in your un-
derstanding the device state at CPU cycle boundaries. The execution of differ-
ent types of instructions in the pipeline is described in section 6.2, Pipeline
Execution of Instruction Types . Figure 6–4(a) shows the execute phases of
the pipeline in sequential order from left to right. Figure 6–4(b) shows the por-
tion of the functional block diagram in which execution occurs.
E4
E6
E7
E5
SMPY
STH
.M1
.D1
8 7
6
5 4
3
2
1
0
Data 1
32
Data memory interface control
16
0
1
2
8
9
Internal data memory
(byte addressable)
E8
E9
E10
E1
STH
.D2
32
15
14
13
12
32
Data 2
16
16
16
3
4
5
6
7
Pipeline Operation Overview
SMPYH
SUB
.M2
.S2
11
10
9
8
7
6
5
4
3
Register file B
Data address 2
TMS320C67x Pipeline
SADD
.L2
2
1
0
32
6-5
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