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Pipeline Operation Overview
5.1 Pipeline Operation Overview
Figure 5–1. Fixed-Point Pipeline Stages
5.1.1
Fetch
5-2
The pipeline phases are divided into three stages:
Fetch
Decode
Execute
All instructions in the 'C62x instruction set flow through the fetch, decode, and
execute stages of the pipeline. The fetch stage of the pipeline has four phases
for all instructions, and the decode stage has two phases for all instructions.
The execute stage of the pipeline requires a varying number of phases,
depending on the type of instruction. The stages of the 'C62x pipeline are
shown in Figure 5–1.
Fetch
The fetch phases of the pipeline are:
PG: Program address generate
PS: Program address send
PW: Program access ready wait
PR: Program fetch packet receive
The 'C62x uses a fetch packet (FP) of eight instructions. All eight of the instruc-
tions proceed through fetch processing together, through the PG, PS, PW, and
PR phases. Figure 5–2(a) shows the fetch phases in sequential order from left
to right. Figure 5–2(b) is a functional diagram of the flow of instructions through
the fetch phases. During the PG phase, the program address is generated in
the CPU. In the PS phase, the program address is sent to memory. In the PW
phase, a memory read occurs. Finally, in the PR phase, the fetch packet is re-
ceived at the CPU. Figure 5–2(c) shows fetch packets flowing through the
phases of the fetch stage of the pipeline. In Figure 5–2(c), the first fetch packet
(in PR) is made up of four execute packets, and the second and third fetch
packets (in PW and PS) contain two execute packets each. The last fetch
packet (in PG) contains a single execute packet of eight instructions.
Decode
Execute
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