6.3.11 4-Cycle Instructions; Intdp Instruction 6 - Texas Instruments TMS320C6000 Series Reference Manual

6.3.11 4-Cycle Instructions

Table 6–26. 4-Cycle Execution
Figure 6–19. 4-Cycle Instruction Phases
6.3.12 INTDP Instruction
Four-cycle instructions use the E1 through E4 phases of the pipeline to com-
plete their operations (see Table 6–26). The following instructions are 4-cycle
instructions:
ADDSP
DPINT
DPSP
DPTRUNC
INTSP
MPYSP
SPINT
SPTRUNC
SUBSP
The sources are read on E1 and the results are written on E4. The 4-cycle in-
structions are executed on the .M or .L units. The status is written to the FMCR
or FADCR on E4. Figure 6–19 shows the pipeline phases the 4-cycle instruc-
tions use.
Pipeline
E1
Stage
src1
Read
src2
Written
Unit in use .L or .M
PG PS PW
The INTDP instruction uses the E1 through E5 phases of the pipeline to com-
plete its operations (see Table 6–27). src2 is read on E1, the lower 32 bits of
the result are written on E4, and the upper 32 bits of the result are written on
E5. The INTDP instruction is executed on the .L units. The status is written to
the FADCR on E4. Figure 6–20 shows the pipeline phases the INTDP instruc-
tions use.
E2
PR DP DC E1
TMS320C67x Pipeline
Functional Unit Hazards
E3 E4
dst
E2 E3 E4
3 delay slots
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