Pipeline Operation: Fetch Packets With Different Numbers Of Execute Packets - Texas Instruments TMS320C6000 Series Reference Manual

Figure 5–18. Pipeline Operation: Fetch Packets With Different Numbers of Execute
Packets
Fetch Execute
packet packet
(FP) (EP) 1
n k
PG
n k+1
n k+2
n+1 k+3
n+2 k+4
n+3 k+5
n+4 k+6
n+5 k+7
n+6 k+8
Clock cycle
2 3 4
É É É
PS PW PR DP
É É É
PG PS PW PR
PG PS PW
PG PS
PG
In Figure 5–18, fetch packet n, which contains three execute packets, is
shown followed by six fetch packets (n + 1 through n + 6), each with one
execute packet (containing eight parallel instructions). The first fetch packet
(n) goes through the program fetch phases during cycles 1–4. During these
cycles, a program fetch phase is started for each of the fetch packets that
follow.
In cycle 5, the program dispatch (DP) phase, the CPU scans the p -bits and
detects that there are three execute packets (k through k + 2) in fetch packet
n. This forces the pipeline to stall, which allows the DP phase to start for
execute packets k + 1 and k + 2 in cycles 6 and 7. Once execute packet k + 2
is ready to move on to the DC phase (cycle 8), the pipeline stall is released.
The fetch packets n + 1 through n + 4 were all stalled so the CPU could have
time to perform the DP phase for each of the three execute packets (k through
k + 2) in fetch packet n. Fetch packet n + 5 was also stalled in cycles 6 and 7:
it was not allowed to enter the PG phase until after the pipeline stall was
released in cycle 8. The pipeline continues operation as shown with fetch
packets n + 5 and n + 6 until another fetch packet containing multiple execu-
tion packets enters the DP phase, or an interrupt occurs.
5 6 7 8
DC E1 E2
É É É É É É
DP DC E1
DP DC
É É É
DP
Pipeline PR
stall PW
PS
PG
Performance Considerations
9 10 11
E3 E4 E5
E2 E3 E4
E1 E2 E3
DC E1 E2
DP DC E1
PR DP DC
PW PR DP
PS PW PR
PG PS PW
TMS320C62x Pipeline
12 13
E5
E4 E5
E3 E4
E2 E3
E1 E2
DC E1
DP DC
PR DP
5-19