Texas Instruments TMS320C6722 User Manual
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Texas Instruments TMS320C6722 User Manual

Texas Instruments TMS320C6722 User Manual

Floating-point digital signal processors
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1 TMS320C6727, TMS320C6726, TMS320C6722 DSPs

1.1 Features

C672x: 32-/64-Bit 300-MHz Floating-Point DSPs
Upgrades to C67x+ CPU From C67x™ DSP
Generation:
– 2X CPU Registers [64 General-Purpose]
– New Audio-Specific Instructions
– Compatible With the C67x CPU
Enhanced Memory System
– 256K-Byte Unified Program/Data RAM
– 384K-Byte Unified Program/Data ROM
– Single-Cycle Data Access From CPU
– Large Program Cache (32K Byte) Supports
RAM, ROM, and External Memory
External Memory Interface (EMIF) Supports
– 100-MHz SDRAM (16- or 32-Bit)
– Asynchronous NOR Flash, SRAM (8-,16-, or
32-Bit)
– NAND Flash (8- or 16-Bit)
Enhanced I/O System
– High-Performance Crossbar Switch
– Dedicated McASP DMA Bus
– Deterministic I/O Performance
dMAX (Dual Data Movement Accelerator)
Supports:
– 16 Independent Channels
– Concurrent Processing of Two Transfer
Requests
– 1-, 2-, and 3-Dimensional
Memory-to-Memory and
Memory-to-Peripheral Data Transfers
– Circular Addressing Where the Size of a
Circular Buffer (FIFO) is not Limited to 2
– Table-Based Multi-Tap Delay Read and
Write Transfers From/To a Circular Buffer
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
C67x, PowerPAD, TMS320C6000, C6000, DSP/BIOS, XDS, TMS320 are trademarks of Texas Instruments.
Philips is a registered trademark of Koninklijki Philips Electronics N.V.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
Three Multichannel Audio Serial Ports
– Transmit/Receive Clocks up to 50 MHz
– Six Clock Zones and 16 Serial Data Pins
– Supports TDM, I2S, and Similar Formats
– DIT-Capable (McASP2)
Universal Host-Port Interface (UHPI)
– 32-Bit-Wide Data Bus for High Bandwidth
– Muxed and Non-Muxed Address and Data
Two 10-MHz SPI Ports With 3-, 4-, and 5-Pin
Options
Two Inter-Integrated Circuit (I2C) Ports
Real-Time Interrupt Counter/Watchdog
Oscillator- and Software-Controlled PLL
Applications:
– Professional Audio
Mixers
Effects Boxes
Audio Synthesis
Instrument/Amp Modeling
Audio Conferencing
Audio Broadcast
Audio Encoder
– Emerging Audio Applications
– Biometrics
– Medical
– Industrial
Commercial or Extended Temperature
144-Pin, 0.5-mm, PowerPAD™ Thin Quad
Flatpack (TQFP) [RFP Suffix]
n
256-Terminal, 1.0-mm, 16x16 Array Plastic Ball
Grid Array (PBGA) [GDH and ZDH Suffixes]
Copyright © 2005–2007, Texas Instruments Incorporated
SPRS268E – MAY 2005 – REVISED JANUARY 2007

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  • Page 1: Tms320C6727, Tms320C6726, Tms320C6722 Dsps

    Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. C67x, PowerPAD, TMS320C6000, C6000, DSP/BIOS, XDS, TMS320 are trademarks of Texas Instruments. Philips is a registered trademark of Koninklijki Philips Electronics N.V.

  • Page 2: Description

    SPRS268E – MAY 2005 – REVISED JANUARY 2007 1.2 Description The TMS320C672x is the next generation of Texas Instruments' C67x generation of high-performance 32-/64-bit floating-point digital signal processors. The TMS320C672x includes the TMS320C6727, TMS320C6726, and TMS320C6722 devices. Enhanced C67x+ CPU. The C67x+ CPU is an enhanced version of the C67x CPU used on the C671x DSPs.
  • Page 3 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 The C6727 extends SDRAM support to 256M-bit and 512M-bit devices. Asynchronous memory support is typically used to boot from a parallel non-multiplexed NOR flash device that can be 8, 16, or 32 bits wide.

  • Page 4: Device Compatibility

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Real-Time Interrupt Timer (RTI). The real-time interrupt timer module includes: Two 32-bit counter/prescaler pairs Two input captures (tied to McASP direct memory access [DMA] events for sample rate measurement) Four compares with automatic update capability Digital Watchdog (optional) for enhanced system robustness Clock Generation (PLL and OSC).

  • Page 5: Functional Block Diagram

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 1.3 Functional Block Diagram Figure 1-1 shows the functional block diagram of the C672x device. Program/Data JTAG EMU 256K Bytes McASP0 Data 16 Serializers C67x+ CPU Program/Data Memory...

  • Page 6: Table Of Contents

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Contents ....TMS320C6727, TMS320C6726, TMS320C6722 Recommended Operating Conditions ............DSPs ......Electrical Characteristics ..........Features ......Parameter Information ..........Description ....... Timing Parameter Symbology .........

  • Page 7: Device Overview

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 2 Device Overview 2.1 Device Characteristics Table 2-1 provides an overview of the C672x DSPs. The table shows significant features of each device, including the capacity of on-chip memory, the peripherals, the execution time, and the package type with pin count.

  • Page 8: Enhanced C67X+ Cpu

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 2.2 Enhanced C67x+ CPU The TMS320C672x floating-point digital signal processors are based on the new C67x+ CPU. This core is code-compatible with the C67x CPU core used on the TMS320C671x DSPs, but with significant enhancements including an increase in core operating frequency from 225 MHz to 300 MHz while operating at 1.2 V.

  • Page 9: Cpu Interrupt Assignments

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 2-2. New Floating-Point Instructions for C67x+ CPU FLOATING-POINT INSTRUCTION IMPROVES OPERATION MPYSPDP SP x DP Faster than MPYDP. Improves high Q biquads (bass management) and FFT. MPYSP2DP SP x SP Faster than MPYDP.

  • Page 10: Internal Program/Data Rom And Ram

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 2.4 Internal Program/Data ROM and RAM The organization of program/data ROM and RAM on C672x is simple and efficient. ROM is organized as two 256-bit-wide pages with four 64-bit-wide banks. RAM is organized as a single 256-bit-wide page with eight 32-bit-wide banks.

  • Page 11: Program Cache

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 2.5 Program Cache The C672x DSP executes code directly from a large on-chip 32K-byte program cache. The program cache has these key features: Wide 256-bit path to internal ROM/RAM Single-cycle access on cache hits 2-cycle miss penalty to internal ROM/RAM Caches external memory as well as ROM/RAM...

  • Page 12: High-Performance Crossbar Switch

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 2.6 High-Performance Crossbar Switch The C672x DSP includes a high-performance crossbar switch that acts as a central hub between bus masters and targets. Figure 2-4 illustrates the connectivity of the crossbar switch.
  • Page 13 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 The five bus masters arbitrate for five different target groups: On-chip memories through the CPU Slave Port (CSP). Memories on the external memory interface (EMIF). Peripheral registers through the peripheral configuration bus.
  • Page 14 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 2-5 shows the bit layout of the device-level bridge control register (CFGBRIDGE) and Table 2-7 contains a description of the bits. Reserved Reserved CSPRST R/W, 1 LEGEND: R/W = Read/Write;...

  • Page 15: Memory Map Summary

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 2.7 Memory Map Summary A high-level memory map of the C672x DSP appears in Table 2-8. The base address of each region is listed. Any address past the end address must not be read or written. The table also lists whether the regions are word-addressable or byte- and word-addressable.

  • Page 16: Boot Modes

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 2.8 Boot Modes The C672x DSP supports only one hardware bootmode option, this is to boot from the internal ROM starting at address 0x0000 0000. Other bootmode options are implemented by a software bootloader stored in ROM.
  • Page 17 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 2-6 shows the bit layout of the CFGPIN0 register and Table 2-10 contains a description of the bits. Reserved PINCAP7 PINCAP6 PINCAP5 PINCAP4 PINCAP3 PINCAP2 PINCAP1...
  • Page 18 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 2-7 shows the bit layout of the CFGPIN1 register and Table 2-11 contains a description of the bits. Reserved PINCAP15 PINCAP14 PINCAP13 PINCAP12 PINCAP11 PINCAP10 PINCAP9...

  • Page 19: Pin Assignments

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 2.9 Pin Assignments 2.9.1 Pin Maps Figure 2-8 Figure 2-9 show the pin assignments on the 256-terminal GDH/ZDH package and the 144-pin RFP package, respectively. EM_WE_ EM_WE EM_D[7]...
  • Page 20 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 SPI0_SIMO EM_CKE SPI0_SOMI/I2C0_SDA EM_CLK AXR0[0] EM_WE_DQM[1] AXR0[1] EM_D[8] AXR0[2] AXR0[3] EM_D[9] EM_D[10] AXR0[4] AXR0[5]/SPI1_SCS EM_D[11] AXR0[6]/SPI1_ENA AXR0[7]/SPI1_CLK EM_D[12] EM_D[13] EM_D[14] AXR0[8]/AXR1[5]/SPI1_SOMI EM_D[15] AXR0[9]/AXR1[4]/SPI1_SIMO EM_D[0] EM_D[1] AXR0[10]/AXR1[3] AXR0[11]/AXR1[2]...

  • Page 21: Terminal Functions

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 2.9.2 Terminal Functions Table 2-12, the Terminal Functions table, identifies the external signal names, the associated pin/ball numbers along with the mechanical package designator, the pin type (I, O, IO, OZ, or PWR), whether the pin/ball has any internal pullup/pulldown resistors, whether the pin/ball is configurable as an IO in GPIO mode, and a functional pin description.
  • Page 22 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 2-12. Terminal Functions (continued) GDH/ SIGNAL NAME TYPE PULL GPIO DESCRIPTION External Memory Interface (EMIF) Data Bus / Universal Host-Port Interface (UHPI) Address Bus Option EM_D[0] EM_D[1] EM_D[2]...
  • Page 23 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 2-12. Terminal Functions (continued) GDH/ SIGNAL NAME TYPE PULL GPIO DESCRIPTION Universal Host-Port Interface (UHPI) Data and Control UHPI_HD[0] UHPI_HD[1] UHPI_HD[2] UHPI_HD[3] UHPI_HD[4] UHPI_HD[5] UHPI_HD[6] UHPI_HD[7]...
  • Page 24 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 2-12. Terminal Functions (continued) GDH/ SIGNAL NAME TYPE PULL GPIO DESCRIPTION McASP0, McASP1, McASP2, and SPI1 Serial Ports AHCLKR0/AHCLKR1 McASP0 and McASP1 Receive Master Clock ACLKR0 McASP0 Receive Bit Clock AFSR0...
  • Page 25 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 2-12. Terminal Functions (continued) GDH/ SIGNAL NAME TYPE PULL GPIO DESCRIPTION Clocks OSCIN 1.2-V Oscillator Input OSCOUT 1.2-V Oscillator Output OSCV Oscillator 1.2-V V tap point (for filter only) OSCV Oscillator V...

  • Page 26: Development

    DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., TMS320C6727GDH250). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX / TMDX) through fully qualified production devices/tools (TMS / TMDS).
  • Page 27 Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
  • Page 28 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 2.10.2.2 Documentation Support Extensive documentation supports the TMS320™ DSP family of devices from product announcement through applications development. The types of documentation available include: data manuals, such as this document, with design specifications;...
  • Page 29 The tools support documentation is electronically available within the Code Composer Studio™ Integrated Development Environment (IDE). For a complete listing of C6000™ DSP latest documentation, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL).

  • Page 30: Device Configurations

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 3 Device Configurations 3.1 Device Configuration Registers The C672x DSP includes several device-level configuration registers, which are listed in Table 3-1. These registers need to be programmed as part of the device initialization procedure. See Section 3.2.

  • Page 31: Peripheral Pin Multiplexing Control

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 3-3 lists the options for configuring the SPI1, McASP0, and McASP1 pins. Note that there are additional finer grain options when selecting which McASP controls the particular AXR serial data pins but these options are not listed here and can be made on a pin by pin basis.
  • Page 32 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 3-5. Priority of Control of Data Output on Multiplexed Pins FIRST PRIORITY SECOND PRIORITY THIRD PRIORITY SPI0_SOMI/I2C0_SDA SPI0_SOMI I2C0_SDA SPI0_CLK/I2C0_SCL SPI0_CLK I2C0_SCL SPI0_SCS/I2C1_SCL SPI0_SCS I2C1_SCL SPI0_ENA/I2C1_SDA...

  • Page 33: Peripheral And Electrical Specifications

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4 Peripheral and Electrical Specifications 4.1 Electrical Specifications This section provides the absolute maximum ratings and the recommended operating conditions for the TMS320C672x DSP. All electrical and switching characteristics in this data manual are valid over the recommended operating conditions unless otherwise specified.

  • Page 34: Electrical Characteristics

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.4 Electrical Characteristics Over Operating Case Temperature Range (Unless Otherwise Noted) PARAMETER TEST CONDITIONS UNIT High Level Output Voltage = –100 µA – 0.2 Low Level Output Voltage = 100 µA High-Level Output Current...

  • Page 35: Parameter Information

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.5 Parameter Information 4.5.1 Parameter Information Device-Specific Information Tester Pin Electronics Data Sheet Timing Reference Point Output 3.5 nH Under Transmission Line Test Z0 = 50 (see note) Device Pin (see note)

  • Page 36: Timing Parameter Symbology

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.6 Timing Parameter Symbology Timing parameter symbols used in the timing requirements and switching characteristics tables are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: Lowercase subscripts and their meanings: Letters and symbols and their meanings:...

  • Page 37: Power Supplies

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.7 Power Supplies For more information regarding TI’s power management products and suggested devices to power TI DSPs, visit www.ti.com/dsppower. 4.7.1 Power-Supply Sequencing This device does not require specific power-up sequencing between the DV and CV voltage rails;...

  • Page 38: Reset

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.8 Reset A hardware reset (RESET) is required to place the DSP into a known good state out of power-up. The RESET signal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core and I/O voltages have reached their proper operating conditions.

  • Page 39: Dual Data Movement Accelerator (Dmax)

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.9 Dual Data Movement Accelerator (dMAX) 4.9.1 dMAX Device-Specific Information The dMAX is a module designed to perform Data Movement Acceleration. The dMAX controller handles user-programmed data transfers between the internal data memory controller and the device peripherals on the C672x DSP.
  • Page 40 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 dMAX High-Priority PaRAM Event Entry #0 Event Event Entry #k Entry Table HiMAX Event Entry #31 HiMAX Reserved Master HiMAX Crossbar (MAX0) Transfer Entry #0 Switch Port Transfer...
  • Page 41 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 The dMAX controller comprises: Event and interrupt processing registers Event encoder High-priority event Parameter RAM (PaRAM) Low-priority event Parameter RAM (PaRAM) Address-generation hardware for High-Priority Events – MAX0 (HiMAX) Address-generation hardware for Low-Priority Events –...
  • Page 42 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-2 lists how the synchronization events are associated with event numbers in the dMAX controller. Table 4-2. dMAX Peripheral Event Input Assignments EVENT NUMBER EVENT ACRONYM EVENT DESCRIPTION DETR[0]...
  • Page 43 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.9.2 dMAX Peripheral Registers Description(s) Table 4-3 is a list of the dMAX registers. Table 4-3. dMAX Configuration Registers BYTE ADDRESS REGISTER NAME DESCRIPTION 0x6000 0008 DEPR Event Polarity Register...

  • Page 44: External Interrupts

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.10 External Interrupts The C672x DSP has no dedicated general-purpose interrupt pins, but the dMAX can be used in combination with a McASP AMUTEIN signal to provide external interrupt capability. There is a multiplexer for each McASP, controlled by the CFGMCASP0/1/2 registers, which allows the AMUTEIN input for that McASP to be sourced from one of seven I/O pins on the DSP.

  • Page 45: External Memory Interface (Emif)

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.11 External Memory Interface (EMIF) 4.11.1 EMIF Device-Specific Information The C672x DSP includes an external memory interface (EMIF) for optional SDRAM, NOR FLASH, NAND FLASH, or SRAM.
  • Page 46 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 C6726/C6722 SDRAM DSP EMIF 2M x 16 x 4 Bank EM_CS[0] EM_CAS EM_RAS EM_WE EM_CLK EM_CKE EM_BA[1:0] BA[1:0] EM_A[11:0] A[11:0] EM_WE_DQM[0] LDQM EM_WE_DQM[1] UDQM EM_D[15:0] DQ[15:0] EM_CS[2]...
  • Page 47 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 C6727 SDRAM DSP EMIF 4M x 16 x 4 Bank EM_CS[0] EM_CAS EM_RAS EM_WE EM_CLK EM_CKE EM_BA[1:0] BA[1:0] EM_A[12:0] A[12:0] EM_WE_DQM[0] LDQM EM_WE_DQM[1] UDQM EM_D[15:0] DQ[15:0] EM_WE_DQM[2]...
  • Page 48 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.11.2 EMIF Peripheral Registers Description(s) Table 4-4 is a list of the EMIF registers. For more information about these registers, see the TMS320C672x DSP External Memory Interface (EMIF) User's Guide (literature number SPRU711). Table 4-4.
  • Page 49 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.11.3 EMIF Electrical Data/Timing Table 4-5 through Table 4-8 assume testing over recommended operating conditions (see Figure 4-7 through Figure 4-13). Table 4-5. EMIF SDRAM Interface Timing Requirements MAX UNIT Input setup time, read data valid on D[31:0] before EM_CLK rising su(EM_DV-EM_CLKH)
  • Page 50 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 (1) (2) Table 4-7. EMIF Asynchronous Interface Timing Requirements MAX UNIT Input setup time, read data valid on EM_D[31:0] before EM_CLK su(EM_DV-EM_CLKH)A rising Input hold time, read data valid on EM_D[31:0] after EM_CLK rising h(EM_CLKH-EM_DIV)A Setup time, EM_WAIT valid before EM_CLK rising edge su(EM_CLKH-EM_WAITV)A...
  • Page 51 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 BASIC SDRAM WRITE OPERATION EM_CLK EM_CS[0] EM_WE_DQM[3:0] EM_BA[1:0] EM_A[12:0] EM_D[31:0] EM_RAS EM_CAS EM_WE Figure 4-7. Basic SDRAM Write Operation BASIC SDRAM READ OPERATION EM_CLK EM_CS[0] EM_WE_DQM[3:0] EM_BA[1:0]...
  • Page 52 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 ASYNCHRONOUS READ WE STROBE MODE SETUP STROBE HOLD EM_CLK EM_CS[2] EM_WE_DQM[3:0] EM_BA[1:0] ADDRESS EM_A[12:0] ADDRESS READ DATA EM_D[31:0] EM_OE EM_WE EM_RW Figure 4-9. Asynchronous Read WE Strobe Mode ASYNCHRONOUS READ SELECT STROBE MODE SETUP...
  • Page 53 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 ASYNCHRONOUS WRITE WE STROBE MODE SETUP STROBE HOLD EM_CLK EM_CS[2] EM_WE_DQM[3:0] BYTE WRITE STROBES EM_BA[1:0] ADDRESS EM_A[12:0] ADDRESS EM_D[31:0] WRITE DATA EM_OE EM_WE EM_RW Figure 4-11.
  • Page 54 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 SETUP STROBE EXTENDED WAIT STATES STROBE HOLD EM_CLK ASSERTED DEASSERTED EM_WAIT Figure 4-13. EM_WAIT Timing Requirements Peripheral and Electrical Specifications Submit Documentation Feedback...

  • Page 55: Universal Host-Port Interface (Uhpi) [C6727 Only]

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.12 Universal Host-Port Interface (UHPI) [C6727 Only] 4.12.1 UHPI Device-Specific Information The C672x DSP includes a flexible universal host-port interface (UHPI) with more options than the host-port interface on the C671x DSP.
  • Page 56 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 4-15 illustrates the Multiplexed Host Address/Data Half-Word Mode hookup between the C672x DSP and an external host microcontroller. In this mode, each 32-bit HPI access is broken up into two halves.
  • Page 57 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 4-16 illustrates the Multiplexed Host Address/Data Fullword Mode hookup between the C672x DSP and an external host microcontroller. In this mode, all 32 bits of UHPI_HD[31:0] are used and the host can access HPIA, HPID, and HPIC in a single bus cycle.
  • Page 58 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 4-17 illustrates the Non-Multiplexed Host Address/Data Fullword mode of the UHPI. In this mode, the UHPI behaves almost like an asynchronous SRAM except it asserts the UHPI_HRDY signal. This mode allows the host to randomly access a 64K-byte page in the C672x address space.
  • Page 59 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.12.2 UHPI Peripheral Registers Description(s) Table 4-11 is a list of the UHPI registers. Table 4-11. UHPI Configuration Registers BYTE ADDRESS REGISTER NAME DESCRIPTION Device-Level Configuration Registers Controlling UHPI 0x4000 0008 CFGHPI...
  • Page 60 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 The UHPI has several device-level configuration registers which affect its behavior. Figure 4-18, Figure 4-19, and Figure 4-20 show the bit layout of these registers. Table 4-12, Table...
  • Page 61 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Reserved HPIAMSB R/W, 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 4-19. CFGHPIAMSB Register Bit Layout (0x4000 000C) Table 4-13.
  • Page 62 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.12.3 UHPI Electrical Data/Timing 4.12.3.1 Universal Host-Port Interface (UHPI) Read and Write Timing Table 4-15 Table 4-16 assume testing over recommended operating conditions (see Figure 4-21 through Figure...
  • Page 63 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 (1) (2) Table 4-16. UHPI Read and Write Switching Characteristics PARAMETER UNIT Case 1. HPIC or HPIA read Case 2. HPID read with no 9 * 2H + 20 auto-increment Case 3.
  • Page 64 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Read Write UHPI_HCS UHPI_HDSx UHPI_HRW UHPI_HA[15:0] Valid Valid UHPI_HD[31:0] Read data (Read) UHPI_HD[31:0] Write data (Write) UHPI_HRDY Depending on the type of write or read operation (HPID or HPIC), transitions on UHPI_HRDY may or may not occur. Figure 4-21.
  • Page 65 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 UHPI_HCS UHPI_HAS UHPI_HCNTL[1:0] UHPI_HRW UHPI_HHWIL HSTROBE UHPI_HD[15:0] UHPI_HRDY Figure 4-14. Depending on the type of write or read operation (HPID without auto-incrementing, HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on UHPI_HRDY may or may not occur.
  • Page 66 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 UHPI_HCS UHPI_HAS UHPI_HCNTL[1:0] UHPI_HRW UHPI_HHWIL HSTROBE UHPI_HD[15:0] UHPI_HRDY Figure 4-14. Depending on the type of write or read operation (HPID without auto-incrementing, HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on UHPI_HRDY may or may not occur.
  • Page 67 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 UHPI_HCS UHPI_HAS UHPI_HCNTL[1:0] UHPI_HRW UHPI_HHWIL HSTROBE UHPI_HD[15:0] UHPI_HRDY Figure 4-14. Depending on the type of write or read operation (HPID without auto-incrementing, HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on UHPI_HRDY may or may not occur.

  • Page 68: Multichannel Audio Serial Ports (Mcasp0, Mcasp1, And Mcasp2)

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.13 Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2) The McASP serial port is specifically designed for multichannel audio applications. Its key features are: Flexible clock and frame sync generation logic and on-chip dividers Up to sixteen transmit or receive data pins and serializers Large number of serial data format options, including:...
  • Page 69 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 The three McASPs on C672x have different configurations (see Table 4-17). NOTE: McASP2 is not available on the C6722. Table 4-17. McASP Configurations on C672x DSP McASP CLOCK PINS DATA PINS...
  • Page 70 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.13.1 McASP Peripheral Registers Description(s) Table 4-18 is a list of the McASP registers. For more information about these registers, see the TMS320C672x DSP Multichannel Audio Serial Port (McASP) Reference Guide (literature number SPRU878).
  • Page 71 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-18. McASP Registers Accessed Through Peripheral Configuration Bus (continued) McASP0 McASP1 McASP2 REGISTER BYTE BYTE BYTE DESCRIPTION NAME ADDRESS ADDRESS ADDRESS 0x4400 00C8 0x4500 00C8 0x4600 00C8 XCLKCHK...
  • Page 72 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-18. McASP Registers Accessed Through Peripheral Configuration Bus (continued) McASP0 McASP1 McASP2 REGISTER BYTE BYTE BYTE DESCRIPTION NAME ADDRESS ADDRESS ADDRESS 0x4400 020C 0x4500 020C –...
  • Page 73 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 4-26 shows the bit layout of the CFGMCASP0 register and Table 4-19 contains a description of the bits. Reserved Reserved AMUTEIN0 R/W, 0 LEGEND: R/W = Read/Write;...
  • Page 74 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 4-27 shows the bit layout of the CFGMCASP1 register and Table 4-20 contains a description of the bits. Reserved Reserved AMUTEIN1 R/W, 0 LEGEND: R/W = Read/Write;...
  • Page 75 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 4-28 shows the bit layout of the CFGMCASP2 register and Table 4-21 contains a description of the bits. Reserved Reserved AMUTEIN2 R/W, 0 LEGEND: R/W = Read/Write;...
  • Page 76 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.13.2 McASP Electrical Data/Timing 4.13.2.1 Multichannel Audio Serial Port (McASP) Timing Table 4-22 Table 4-23 assume testing over recommended operating conditions (see Figure 4-29 Figure 4-30).
  • Page 77 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-23. McASP Switching Characteristics PARAMETER UNIT Cycle time, AHCLKR internal, AHCLKR output Cycle time, AHCLKR external, AHCLKR output c(AHCKRX) Cycle time, AHCLKX internal, AHCLKX output Cycle time, AHCLKX external, AHCLKX output Pulse duration, AHCLKR internal, AHCLKR output (AHR/2) –...
  • Page 78 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) ACLKR/X (CLKRP = CLKXP = 0) ACLKR/X (CLKRP = CLKXP = 1) AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) AFSR/X (Slot Width, 0 Bit Delay)
  • Page 79 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) ACLKR/X (CLKRP = CLKXP = 1) ACLKR/X (CLKRP = CLKXP = 0) AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) AFSR/X (Slot Width, 0 Bit Delay)

  • Page 80: Serial Peripheral Interface Ports (Spi0, Spi1)

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.14 Serial Peripheral Interface Ports (SPI0, SPI1) 4.14.1 SPI Device-Specific Information Figure 4-31 is a block diagram of the SPI module, which is a simple shift register and buffer plus control logic.
  • Page 81 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Optional − Slave Chip Select SPIx_SCS SPIx_SCS Optional Enable (Ready) SPIx_ENA SPIx_ENA SPIx_CLK SPIx_CLK SPIx_SOMI SPIx_SOMI SPIx_SIMO SPIx_SIMO MASTER SPI SLAVE SPI Figure 4-32. Illustration of SPI Master-to-SPI Slave Connection Submit Documentation Feedback Peripheral and Electrical Specifications...
  • Page 82 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.14.2 SPI Peripheral Registers Description(s) Table 4-24 is a list of the SPI registers. Table 4-24. SPIx Configuration Registers SPI0 SPI1 REGISTER NAME DESCRIPTION BYTE ADDRESS BYTE ADDRESS 0x4700 0000...
  • Page 83 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.14.3 SPI Electrical Data/Timing 4.14.3.1 Serial Peripheral Interface (SPI) Timing Table 4-25 through Table 4-32 assume testing over recommended operating conditions (see Figure 4-33 through Figure 4-36).
  • Page 84 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-26. General Timing Requirements for SPIx Slave Modes MAX UNIT greater of 8P or Cycle Time, SPIx_CLK, All Slave Modes 256P c(SPC)S 100 ns greater of 4P or Pulse Width High, SPIx_CLK, All Slave Modes w(SPCH)S...
  • Page 85 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 (2) (3) Table 4-27. Additional SPI Master Timings, 4-Pin Enable Option MAX UNIT Polarity = 0, Phase = 0, 3P + 15 to SPIx_CLK rising Polarity = 0, Phase = 1, 0.5t + 3P + 15...
  • Page 86 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 (2) (3) Table 4-29. Additional SPI Master Timings, 5-Pin Option MAX UNIT Polarity = 0, Phase = 0, 0.5t c(SPC)M from SPIx_CLK falling Max delay for slave to Polarity = 0, Phase = 1, deassert SPIx_ENA after from SPIx_CLK falling...
  • Page 87 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 (2) (3) Table 4-30. Additional SPI Slave Timings, 4-Pin Enable Option MAX UNIT Polarity = 0, Phase = 0, P – 10 3P + 15 from SPIx_CLK falling Polarity = 0, Phase = 1, 0.5t...
  • Page 88 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 (2) (3) Table 4-32. Additional SPI Slave Timings, 5-Pin Option UNIT Required delay from SPIx_SCS asserted at slave to first d(SCSL_SPC)S SPIx_CLK edge at slave. Polarity = 0, Phase = 0, 0.5t + P + 10...
  • Page 89 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 MASTER MODE POLARITY = 0 PHASE = 0 SPIx_CLK SPI_SIMO MO(0) MO(1) MO(n−1) MO(n) SPI_SOMI MI(0) MI(1) MI(n−1) MI(n) MASTER MODE POLARITY = 0 PHASE = 1 SPIx_CLK SPI_SIMO MO(0)
  • Page 90 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 SLAVE MODE POLARITY = 0 PHASE = 0 SPIx_CLK SPI_SIMO SI(0) SI(1) SI(n−1) SI(n) SPI_SOMI SO(0) SO(1) SO(n−1) SO(n) SLAVE MODE POLARITY = 0 PHASE = 1 SPIx_CLK SPI_SIMO SI(0)
  • Page 91 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 MASTER MODE 4 PIN WITH ENABLE SPIx_CLK SPI_SIMO MO(0) MO(n−1) MO(n) MO(1) SPI_SOMI MI(0) MI(1) MI(n−1) MI(n) SPIx_ENA MASTER MODE 4 PIN WITH CHIP SELECT SPIx_CLK SPI_SIMO MO(0)
  • Page 92 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 SLAVE MODE 4 PIN WITH ENABLE SPIx_CLK SPI_SOMI SO(0) SO(1) SO(n−1) SO(n) SPI_SIMO SI(0) SI(1) SI(n−1) SI(n) SPIx_ENA SLAVE MODE 4 PIN WITH CHIP SELECT SPIx_CLK SO(n−1) SPI_SOMI...

  • Page 93: Inter-Integrated Circuit Serial Ports (I2C0, I2C1)

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.15 Inter-Integrated Circuit Serial Ports (I2C0, I2C1) 4.15.1 I2C Device-Specific Information Having two I2C modules on the C672x simplifies system architecture, since one module may be used by the DSP to control local peripherals ICs (DACs, ADCs, etc.) while the other may be used to communicate with other controllers in a system or to implement a user interface.
  • Page 94 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.15.2 I2C Peripheral Registers Description(s) Table 4-33 is a list of the I2C registers. Table 4-33. I2Cx Configuration Registers I2C0 I2C1 REGISTER NAME DESCRIPTION BYTE ADDRESS BYTE ADDRESS 0x4900 0000...
  • Page 95 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.15.3 I2C Electrical Data/Timing 4.15.3.1 Inter-Integrated Circuit (I2C) Timing Table 4-34 Table 4-35 assume testing over recommended operating conditions (see Figure 4-38 Figure 4-39). Table 4-34.
  • Page 96 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-35. I2C Switching Characteristics (continued) PARAMETER UNIT Standard Mode Pulse duration, I2Cx_SCL low w(SCLL) Fast Mode Standard Mode Pulse duration, I2Cx_SCL high w(SCLH) Fast Mode Standard Mode Setup time, I2Cx_SDA valid before I2Cx_SCL...

  • Page 97: Real-Time Interrupt (Rti) Timer With Digital Watchdog

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.16 Real-Time Interrupt (RTI) Timer With Digital Watchdog 4.16.1 RTI/Digital Watchdog Device-Specific Information C672x includes an RTI timer module which is used to generate periodic interrupts. This module also includes an optional digital watchdog feature.
  • Page 98 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 The digital watchdog is disabled by default. Once enabled, a sequence of two 16-bit key values (0xE51A followed by 0xA35C in two separate writes) must be continually written to the key register before the watchdog counter counts down to zero;...
  • Page 99 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-36. RTI Registers (continued) BYTE ADDRESS REGISTER NAME DESCRIPTION 0x4200 0088 RTIINTFLAG Interrupt Flags. Interrupt pending bits. 0x4200 0090 RTIDWDCTRL Digital Watchdog Control. Enables the Digital Watchdog. 0x4200 0094 RTIDWDPRLD Digital Watchdog Preload.

  • Page 100: External Clock Input From Oscillator Or Clkin Pin

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.17 External Clock Input From Oscillator or CLKIN Pin The C672x device includes two choices to provide an external clock input, which is fed to the on-chip PLL to generate high-frequency system clocks.
  • Page 101 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.17.1 Clock Electrical Data/Timing Table 4-39 assumes testing over recommended operating conditions. Table 4-39. CLKIN Timing Requirements UNIT Oscillator frequency range (OSCIN/OSCOUT) Cycle time, external clock driven on CLKIN c(CLKIN) Pulse width, CLKIN high 0.4t...

  • Page 102: Phase-Locked Loop (Pll)

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.18 Phase-Locked Loop (PLL) 4.18.1 PLL Device-Specific Information The C672x DSP generates the high-frequency internal clocks it requires through an on-chip PLL. The input to the PLL is either from the on-chip oscillator (OSCIN pin) or from an external clock on the CLKIN pin.
  • Page 103 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-40. Allowed PLL Operating Conditions ALLOWED SETTING OR RANGE PARAMETER DEFAULT VALUE PLLRST = 1 assertion time during initialization 125 ns Lock time before setting PLLEN = 1. After changing D0, PLLM, or 187.5 µs input clock.
  • Page 104 TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.18.2 PLL Registers Description(s) Table 4-41 is a list of the PLL registers. For more information about these registers, see the TMS320C672x DSP Software-Programmable Phase-Locked Loop (PLL) Controller Reference Guide (literature number SPRU879).

  • Page 105: Application Example

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 5 Application Example Figure 5-1 illustrates a high-level block diagram of the device and other devices to which it may typically connect. See Section 1.2 for an overview of each major block.

  • Page 106: Revision History

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 6 Revision History This data sheet revision history highlights the technical changes made to the SPRS268D device-specific data sheet to make it an SPRS268E revision. Scope: Corrected addresses of the XGBLCTL register in Table...

  • Page 107: Mechanical Data

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 7 Mechanical Data 7.1 Package Thermal Resistance Characteristics Table 7-1 Table 7-2 provide the thermal characteristics for the recommended package types used on the TMS320C672x DSP. Table 7-1.

  • Page 108: Supplementary Information About The 144-Pin Rfp Powerpad™ Package

    TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 7.2 Supplementary Information About the 144-Pin RFP PowerPAD™ Package 7.2.1 Standoff Height This section highlights a few important details about the 144-pin RFP PowerPAD™ package. Texas Instruments' PowerPAD Thermally Enhanced Package Technical Brief (literature number SLMA002)
  • Page 109 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 7.2.2 PowerPAD™ PCB Footprint Texas Instruments' PowerPAD Thermally Enhanced Package Technical Brief (literature number SLMA002) should be consulted when creating a PCB footprint for this device. In general, for proper thermal performance, the thermal pad under the package body should be as large as possible.

  • Page 111: Packaging Information

    PACKAGE OPTION ADDENDUM www.ti.com 4-May-2009 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Type Drawing TMX320C6722RFP OBSOLETE HTQFP Call TI Call TI TMX320C6726RFP OBSOLETE HTQFP Call TI Call TI TMX320C6727GDH OBSOLETE Call TI Call TI TMX320C6727ZDH OBSOLETE...
  • Page 114 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

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