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3.5 Parallel Operations
Figure 3–2. Basic Format of a Fetch Packet
31
0 31
p
Instruction
Instruction
A
LSBs of
the byte
00000 2
address
Instructions are always fetched eight at a time. This constitutes a fetch packet .
The basic format of a fetch packet is shown in Figure 3–2. Fetch packets are
aligned on 256-bit (8-word) boundaries.
0 31
0 31
p
p
Instruction
B
C
00100 2
01000 2
The execution of the individual instructions is partially controlled by a bit in
each instruction, the p -bit. The p -bit (bit 0) determines whether the instruction
executes in parallel with another instruction. The p -bits are scanned from left
to right (lower to higher address). If the p -bit of instruction i is 1, then instruction
i + 1 is to be executed in parallel with (in the the same cycle as) instruction i .
If the p -bit of instruction i is 0, then instruction i + 1 is executed in the cycle after
instruction i . All instructions executing in parallel constitute an execute packet .
An execute packet can contain up to eight instructions. Each instruction in an
execute packet must use a different functional unit.
An execute packet cannot cross an 8-word boundary. Therefore, the last p- bit
in a fetch packet is always set to 0, and each fetch packet starts a new execute
packet. There are three types of p -bit patterns for fetch packets. These three
p -bit patterns result in the following execution sequences for the eight instruc-
tions:
Fully serial
Fully parallel
Partially serial
Example 3–1 through Example 3–3 illustrate the conversion of a p- bit se-
quence into a cycle-by-cycle execution stream of instructions.
0 31
0 31
p
p
Instruction
Instruction
D
E
01100 2
10000 2
TMS320C62x/C67x Fixed-Point Instruction Set
Parallel Operations
0 31
0 31
p
p
Instruction
Instruction
F
G
10100 2
11000 2
0
p
Instruction
H
11100 2
3-13
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