Texas Instruments TMS320C6000 Series Reference Manual page 390

Index
operations occurring during 5-7
used during memory accesses 5-22, 6-56
PR pipeline phase 5-2, 6-2
program access ready wait. See PW pipeline phase
program address generate. See PG pipeline phase
program address send. See PS pipeline phase
program counter (PCE1) 2-8, 2-12, 3-40
figure 2-12
program fetch counter (PFC) 3-40
program fetch packet receive. See PR pipeline
phase
program memory accesses, versus data load
accesses 5-22, 6-56
PS pipeline phase 5-2, 6-2
push, definition A-3
PW pipeline phase 5-2, 6-2
PWRD field (CSR) 2-11
R
RCPDP instruction 4-61 to 4-62
RCPSP instruction 4-63 to 4-64
register files
cross paths 2-7
data address paths 2-7
general-purpose 2-4
memory, load, and store paths 2-7
relationship to data paths 2-7
register storage scheme, 40-bit data, figure 2-5
registers
AMR. See addressing mode register (AMR)
CSR. See control status register (CSR)
FADCR. See floating-point adder configuration
register (FADCR)
FAUCR. See floating-point auxiliary configuration
register (FAUCR)
FMCR. See floating-point multiplier configuration
register (FMCR)
ICR. See interrupt clear register (ICR)
IER. See interrupt enable register (IER)
IFR. See interrupt flag register (IFR)
IRP. See interrupt return pointer (IRP)
ISR. See interrupt set register (ISR)
ISTP. See interrupt service table pointer (ISTP)
NRP. See nonmaskable interrupt return pointer
(NRP)
PCE1. See program counter (PCE1)
Index-8
read constraints 3-19
write constraints 3-19
relocation of the interrupt service table (IST) 7-9
reset interrupt 7-3
RESET signal
as an interrupt 7-3
CPU state after 7-16
resource constraints 3-17
using the same functional unit 3-17
returning from a trap 7-27
returning from interrupt servicing 7-16
returning from maskable interrupt 7-17
returning from NMI 7-16
RSQRDP instruction 4-65 to 4-67
RSQRSP instruction 4-68 to 4-70
S
.S functional units 2-6
.S unit hazards
2-cycle DP instruction 6-23
branch instruction 6-24
DP compare instruction 6-22
single-cycle instruction 6-21
SADD instruction 3-101 to 3-103
SAT field (CSR) 2-11
SAT instruction 3-104 to 3-105
serial fetch packets 3-14
serial ports 1-9
SET instruction 3-106 to 3-108
setting an individual interrupt, example 7-15
setting interrupts 7-14
setting the interrupt flag 7-18, 7-22
SHL instruction 3-109 to 3-110
SHR instruction 3-111 to 3-112
SHRU instruction 3-113 to 3-114
single-cycle instructions
.L-unit instruction hazards 6-30
.S-unit instruction hazards 6-21
.D-unit instruction hazards 6-36
execution 6-38
execution block diagram 6-38
figure of phases 6-38
pipeline operation 6-38
single-cycle instructions
execution block diagram 5-12
figure of phases 5-12