Page 1 TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide Literature Number: SPRU629 April 2003...
Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
Page 3: Read This First
Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. Related Documentation From Texas Instruments The following documents describe the C6000 tools. Copies of these documents are available on the Internet at www.ti.com.
Page 4 Trademarks Related Documentation From Texas Instruments / Trademarks Code Composer Studio Application Programming Interface Reference Guide (literature number SPRU321) describes the Code Composer Studio program custom plug-ins for Code Composer. TMS320C6x Peripheral Support Library Programmer’s Reference (literature number SPRU273) describes the contents of the...
Page 5: Table Of Contents
Overview ............... . Provides an overview of the video port peripheral in the digital signal processors (DSPs) of the TMS320C6000 DSP family.
Page 6 Contents Video Port Throughput and Latency 2.6.1 Video Capture Throughput 2.6.2 Video Display Throughput Video Port Control Registers 2.7.1 Video Port Control Register (VPCTL) 2.7.2 Video Port Status Register (VPSTAT) 2.7.3 Video Port Interrupt Enable Register (VPIE) 2.7.4 Video Port Interrupt Status Register (VPIS) Video Capture Port .
Page 7 TSI Capture Mode ............3.8.1 TSI Capture Features 3.8.2...
Page 8 Contents Video Display Port ............. . . Discusses the video display port.
Page 9 4.12.6 Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) 4.12.7 Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) 4.12.8 Video Display Field 2 Vertical Blanking End Register (VDVBLKE2) 4.12.9 Video Display Field 1 Image Offset Register (VDIMGOFF1) 4.12.10 Video Display Field 1 Image Size Register (VDIMGSZ1) 4.12.11 Video Display Field 2 Image Offset Register (VDIMGOFF2) 4.12.12 Video Display Field 2 Image Size Register (VDIMGSZ2) 4.12.13 Video Display Field 1 Timing Register (VDFLDT1)
Page 10 Contents VCXO Interpolated Control Port Provides an overview of the VCXO interpolated control (VIC) port. Overview ..............Interface .
Page 11 1–1 Video Port Block Diagram ............1–2 BT.656 Video Capture FIFO Configuration 1–3...
Page 12 Figures 3–21 20-Bit Raw Data FIFO Packing 3–22 Parallel TSI Capture ............3–23 Program Clock Reference (PCR) Header Format 3–24...
Page 13 4–17 10-Bit Y/C FIFO Unpacking ........... . 4–18 10-Bit Y/C Dense FIFO Unpacking 4–19...
Page 14 Figures 4–61 Video Display Clipping Register (VDCLIP) 4–62 Video Display Default Display Value Register (VDDEFVAL) 4–63 Video Display Default Display Value Register (VDDEFVAL)—Raw Data Mode 4–64 Video Display Vertical Interrupt Register (VDVINT) 4–65 Video Display Field Bit Register (VDFBIT) 4–66 Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1) 4–67 Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2)
Page 15 1–1 Video Capture Signal Mapping 1–2 Video Display Signal Mapping 1–3 VDIN Data Bus Usage for Capture Modes 1–4 VDOUT Data Bus Usage for Display Modes 2–1 Video Port Functional Clocks 2–2 Y/C Video Capture FIFO Capacity 2–3 Raw Video Display FIFO Capacity 2–4 Video Port Control Registers 2–5...
Page 16 Tables 3–24 TSI Capture Control Register (TSICTL) Field Descriptions 3–25 TSI Clock Initialization LSB Register (TSICLKINITL) Field Descriptions 3–26 TSI Clock Initialization MSB Register (TSICLKINITM) Field Descriptions 3–27 TSI System Time Clock LSB Register (TSISTCLKL) Field Descriptions 3–28 TSI System Time Clock MSB Register (TSISTCLKM) Field Descriptions 3–29 TSI System Time Clock Compare LSB Register (TSISTCMPL) Field Descriptions 3–30...
Page 17 4–26 Video Display Counter Reload Register (VDRELOAD) Field Descriptions 4–27 Video Display Display Event Register (VDDISPEVT) Field Descriptions 4–28 Video Display Clipping Register (VDCLIP) Field Descriptions 4–29 Video Display Default Display Value Register (VDDEFVAL) Field Descriptions 4–30 Video Display Vertical Interrupt Register (VDVINT) Field Descriptions 4–31 Video Display Field Bit Register (VDFBIT) Field Descriptions 4–32...
Page 18: Overview
This chapter provides an overview of the video port peripheral in the digital signal processors (DSPs) of the TMS320C6000 DSP family. Included are an overview of the video port functions, FIFO configurations, and signal mapping. Topic Video Port ........... . Video Port FIFO .
Page 19: Video Port
Video Port 1.1 Video Port The video port peripheral can operate as a video capture port, video display port, or transport stream interface (TSI) capture port. It provides the following functions: Video capture mode: Capture rate up to 80 MHz. Two channels of 8/10-bit digital video input from a digital camera or analog camera (using a video decoder).
Page 20 TSI capture mode: Transport stream interface (TSI) from a front-end device such as demodulator or forward error correction device in 8-bit parallel format at up to 30 Mbytes/sec. The port generates up to three events per channel and one interrupt to the DSP.
Page 21: Video Port Block Diagram
Video Port Figure 1–1. Video Port Block Diagram VCLK1 VCLK2 Timing and VCTL1 control logic VCTL2 VCTL3 BT.656 capture pipeline Y/C video VDIN[19–0] capture pipeline Raw video capture pipeline TSI capture pipeline BT.656 capture pipeline Raw video capture pipeline VDIN[19–10] Overview Internal peripheral bus Memory...
Page 22: Video Port Fifo
1.2 Video Port FIFO The video port includes a FIFO to store data coming into or out from the video port. The video port operates in conjunction with DMA transfers to move data between the video port FIFO and external or on-chip memory. You can pro- gram threshold settings so DMA events are generated when the video port FIFO reaches a certain fullness (for capture) or goes below a certain fullness (for display).
Page 23: Video Capture Fifo Configurations
Video Port FIFO 1.2.2 Video Capture FIFO Configurations During video capture operation, the video port FIFO has one of four configura- tions depending on the capture mode. For BT.656 operation, the FIFO is split into channel A and B, as shown in Figure 1–2. Each FIFO is clocked indepen- dently with the channel A FIFO receiving data from the VDIN[9–0] half of the bus and the channel B FIFO receiving data from the VDIN[19–10] half of the bus.
Page 24: Bit Raw Video Capture And Tsi Video Capture Fifo Configuration
For 8/10-bit raw video, the FIFO is split into channel A and B, as shown in Figure 1–3. Each FIFO is clocked independently with the channel A FIFO receiving data from the VDIN[9–0] half of the bus and the channel B FIFO receiving data from the VDIN[19–10] half of the bus.
Page 25: Y/C Video Capture Fifo Configuration
Video Port FIFO For Y/C video capture, the FIFO is configured as a single channel split into sep- arate Y, Cb, and Cr buffers with separate write pointers and read registers (YSRCA, CBSRCA, and CRSRCA). Figure 1–4 shows how Y data is received on the VDIN[9–0] half of the bus and Cb/Cr data is received on the VDIN[19–10] half of the bus and demultiplexed into the Cb and Cr buffers.
Page 26: Video Display Fifo Configurations
For 16/20-bit raw video, the FIFO is configured as a single buffer, as shown in Figure 1–5. The FIFO receives 16/20-bit data from the VDIN[19–0] bus. The FIFO has a single write pointer and read register (YSRCA). Figure 1–5. 16/20-Bit Raw Video Capture FIFO Configuration VDIN[19–0] 16/20 1.2.3...
Page 27: Bit Raw Video Display Fifo Configuration
Video Port FIFO For 8/10-bit raw video, the FIFO is configured as a single buffer as shown in Figure 1–7. The FIFO outputs data on the VDOUT[9–0] half of the bus. The FIFO has a single read pointer and write register (YDSTA). Figure 1–7.
Page 28: Bit Locked Raw Video Display Fifo Configuration
Figure 1–8. 8/10 Bit Locked Raw Video Display FIFO Configuration YDSTA YDSTB For 16/20-bit raw video, the FIFO is configured as a single buffer, as shown in Figure 1–9. The FIFO outputs data on VDOUT[19–0]. The FIFO has a single read pointer and write register (YDSTA).
Page 29: Video Port Registers
Video Port Registers Video Port FIFO / Video Port Registers For Y/C video display, the FIFO is configured as a single channel split into sep- arate Y, Cb, and Cr buffers with separate read pointers and write registers (YDSTA, CBDST, and CRDST). Figure 1–10 shows how Y data is output on the VDOUT[9–0] half of the bus and Cb/Cr data is multiplexed and output on the VDOUT[19–10] half of the bus.
Page 30: Video Port Pin Mapping
1.4 Video Port Pin Mapping The video port requires 21 external signal pins for full functionality. Pin usage and direction changes depend on the selected operating mode. Pin functional- ity detail for video capture mode is listed in Table 1–1. Pin functionality detail for video display mode is listed in Table 1–2.
Page 31: Video Display Signal Mapping
Video Port Pin Mapping Table 1–2. Video Display Signal Mapping Video Port BT.656 Signal Display Mode VDATA[9–0] VDOUT[9–0] (Out) VDATA[19–10] Not Used VCLK1 VCLKIN (In) VCLK2 VCLKOUT (Out) VCTL1 HSYNC/HBLNK/ AVID/FLD (Out) or HSYNC (In) VCTL2 VSYNC/VBLNK/ CSYNC/FLD (Out) or VSYNC (In) VCTL3 CBLNK/FLD (Out) CBLNK/FLD (Out)
Page 32: Vdin Bus Usage For Capture Modes
1.4.1 VDIN Bus Usage for Capture Modes The alignment and usage of data on the VDIN bus depends on the capture mode as shown in Table 1–3. Table 1–3. VDIN Data Bus Usage for Capture Modes BT.656 Data Bus 10-Bit 8-Bit 10-Bit VDIN19...
Page 33: Vdout Data Bus Usage For Display Modes
Video Port Pin Mapping 1.4.2 VDOUT Data Bus Usage for Display Modes The alignment and usage of data on the VDOUT bus depends on the display mode as shown in Table 1–4. Table 1–4. VDOUT Data Bus Usage for Display Modes BT.656 Data Bus 10-Bit...
Page 34: Video Port
This chapter discusses the basic operation of the video port. Included is a discussion of the sources and types of resets, interrupt operation, DMA opera- tion, external clock inputs, video port throughput and latency, and the video port control registers. Topic Reset Operation .
Page 35: Reset Operation
Reset Operation 2.1 Reset Operation The video port has several sources and types of resets. The actions performed by these resets and the state of the port following the resets is described in the following sections. 2.1.1 Power-On Reset Power-on reset is an asynchronous hardware reset caused by a chip-level reset operation.
Page 36: Software Port Reset
If software sets the PEREN bit in PCR but the VPHLT bit in VPCTL remains set: VCLK1, VCLK2, and STCLK are enabled to the port (allowing logic reset to complete). Peripheral bus accesses are acknowledged (RREADY/WREADY returned) to prevent DMA lock-up. (Any value returned on reads, data accepted or discarded on writes.) Peripheral bus MMR interface allows access to all registers.
Page 37: Display Channel Reset
Reset Operation Once the port is configured and the VCEN bit is set, the setting of other VCxCTL bits (except VCEN, RSTCH, and BLKCAP) is prohibited and the capture counters begin counting. When BLKCAP is cleared, data capture and event generation may begin. 2.1.5 Display Channel Reset A software reset may be performed on the display channel by setting the...
Page 38: Interrupt Operation
2.2 Interrupt Operation The video port can generate an interrupt to the DSP core after any of the follow- ing events occur: Capture complete (CCMPx) bit is set. Capture overrun (COVRx) bit is set. Synchronization byte error (SERRx) bit is set. Vertical interrupt (VINTxn) bit is set.
Page 39: Dma Operation
DMA Operation 2.3 DMA Operation The video port uses up to three DMA events per channel for a total of six possible events. Each DMA event uses a dedicated event output. The outputs are: VPYEVTA VPCbEVTA VPCrEVTA VPYEVTB VPCbEVTB VPCrEVTB 2.3.1 Capture DMA Event Generation Capture DMA events are generated based on the state of the capture FIFO(s).
Page 40: Capture Dma Event Generation Flow Diagram
Figure 2–1. Capture DMA Event Generation Flow Diagram Empty FIFO Capture data, no DMA pending FIFO threshold Generate DMA event Capture data, DMA pend- ing, new events disabled Pending DMA begun Capture data, DMA active, new events enabled FIFO 2x threshold Generate DMA request Capture Data, DMA active &...
Page 41: Display Dma Event Generation
DMA Operation Because the capture FIFOs may hold multiple thresholds worth of data, a problem arises at the boundaries between fields. Since Field 1 and Field 2 may have different threshold values, the amount of data in the FIFO required to generate the DMA event changes depending on the current capture field and the field of any outstanding DMA requests.
Page 42: Display Dma Event Generation Flow Diagram
Figure 2–2. Display DMA Event Generation Flow Diagram Start of field FIFO empty Generate DMA event, new events disabled Pending DMA begun ? FIFO underrun ? Underrun error SPRU629 Display data, no DMA pending FIFO space threshold Event counter expired ? Generate DMA event Display data, DMA pending, new events...
Page 43: Dma Size And Threshold Restrictions
DMA Operation A DMA event counter is used to track the number of DMA events generated in each field as programmed in the VDDISPEVT register. The DISPEVT1 or DISPEVT2 value (depending on the current display field) is loaded at the start of each field.
Page 44: Dma Interface Operation
DMA Operation Similarly if a subhorizontal line length is desired (½ line, for example), then the line length and threshold must be chosen such that the threshold is divisible by 2. (This can also be stated as the line length must be an even multiple of #DMAs/line 8).
Page 45: Clocks
Clocks Clocks / Video Port Functionality Subsets 2.4 Clocks The video port has three external clock inputs as shown in Table 2–1. No synchronization is required between the clocks sourced by the external pins. VCLK1 and VCLK2 clock frequencies should be less than the DMA interface clock.
Page 46: Fifo Size
2.5.2 FIFO Size Some low-cost device implementations with narrow video ports width or restricted to lower video frequency operations may use a reduced FIFO size. FIFO size does not affect the DMA request mechanism. The selection of 8-bit or 10-bit port width automatically cuts the FIFO size in half with support for only a single channel of operation.
Page 47: Y/C Video Capture Fifo Capacity
Video Port Throughput and Latency Table 2–2. Y/C Video Capture FIFO Capacity Sample Y Samples Cb Samples Cr Samples Using these values and the formula above, the maximum time to empty the FIFO (t ) may be calculated for each case. The DMA output rate (r calculated as the FIFO size divided by t 8-bit (n = 1): 10-bit dense (n = 1): t...
Page 48: Video Display Throughput
2.6.2 Video Display Throughput Video display throughput may be calculated in a manner similar to video capture. In this case, the time to fill the display FIFO must be less than the time to empty the FIFO or underflow occurs. The 110 MHz display rate supports a maximum display resolution of 1280 horizontal blanking time is ~3.88 s.
Page 49: Video Port Control Registers
Video Port Control Registers A DMA write throughput of at least 330 MBytes/s is required for the highest display rate operation supported by 20-bit implementations of the video port. C64x devices including the video port typically have more than enough DMA bandwidth to support this throughput requirement.
Page 50: Video Port Control Register (Vpctl)
2.7.1 Video Port Control Register (VPCTL) The video port control register (VPCTL) determines the basic operation of the video port. The VPCTL is shown in Figure 2–3 and described in Table 2–5. Not all combinations of the port control bits are unique. The control bit encoding is shown in Table 2–6.
Page 51 Video Port Control Registers Table 2–5. Video Port Control Register (VPCTL) Field Descriptions (Continued) † † field symval Value VPHLT NONE CLEAR 13–8 Reserved – VCLK2P NONE REVERSE VCT3P NONE ACTIVELOW VCT2P NONE ACTIVELOW VCT1P NONE ACTIVELOW Reserved – † For CSL implementation, use the notation VP_VPCTL_field_symval 2-18 Video Port Description...
Page 52: Video Port Operating Mode Selection
Table 2–5. Video Port Control Register (VPCTL) Field Descriptions (Continued) † † field symval Value NONE CAPTURE DISP CAPTURE DISPLAY DCHNL SINGLE DUAL † For CSL implementation, use the notation VP_VPCTL_field_symval Table 2–6. Video Port Operating Mode Selection VPCTL Bit DISP DCHNL Single channel video capture.
Page 53: Video Port Status Register (Vpstat)
Video Port Control Registers 2.7.2 Video Port Status Register (VPSTAT) The video port status register (VPSTAT) indicates the current condition of the video port. The VPSTAT is shown in Figure 2–4 and described in Table 2–7. Figure 2–4. Video Port Status Register (VPSTAT) Reserved Legend: R = Read only;...
Page 54: Video Port Interrupt Enable Register (Vpie)
2.7.3 Video Port Interrupt Enable Register (VPIE) The video port interrupt enable register (VPIE) enables sources of the video port interrupt to the DSP. The VPIE is shown in Figure 2–5 and described in Table 2–8. Figure 2–5. Video Port Interrupt Enable Register (VPIE) LFDB SFDB VINTB2...
Page 55 Video Port Control Registers Table 2–8. Video Port Interrupt Enable Register (VPIE) Field Descriptions (Continued) † † field symval Value VINTB1 DISABLE ENABLE SERRB DISABLE ENABLE CCMPB DISABLE ENABLE COVRB DISABLE ENABLE GPIO DISABLE ENABLE Reserved – DCNA DISABLE ENABLE DCMP DISABLE ENABLE...
Page 56 Table 2–8. Video Port Interrupt Enable Register (VPIE) Field Descriptions (Continued) † † field symval Value DISABLE ENABLE 9–8 Reserved – LFDA DISABLE ENABLE SFDA DISABLE ENABLE VINTA2 DISABLE ENABLE VINTA1 DISABLE ENABLE SERRA DISABLE ENABLE CCMPA DISABLE ENABLE COVRA DISABLE ENABLE DISABLE...
Page 57: Video Port Interrupt Status Register (Vpis)
Video Port Control Registers 2.7.4 Video Port Interrupt Status Register (VPIS) The video port interrupt status register (VPIS) displays the status of video port interrupts to the DSP. The interrupt is only sent to the DSP if the corresponding enable bit in VPIE is set. All VPIS bits are cleared by writing a 1, writing a 0 has no effect.
Page 58 Table 2–9. Video Port Interrupt Status Register (VPIS) Field Descriptions (Continued) field symval Value SFDB NONE CLEAR VINTB2 NONE CLEAR VINTB1 NONE CLEAR SERRB NONE CLEAR † For CSL implementation, use the notation VP_VPIS_field_symval SPRU629 Video Port Control Registers Description Short field detected on channel B interrupt detected bit.
Page 59 Video Port Control Registers Table 2–9. Video Port Interrupt Status Register (VPIS) Field Descriptions (Continued) field symval Value CCMPB NONE CLEAR COVRB NONE CLEAR GPIO NONE CLEAR Reserved – DCNA NONE CLEAR † For CSL implementation, use the notation VP_VPIS_field_symval 2-26 Video Port Description...
Page 60 Table 2–9. Video Port Interrupt Status Register (VPIS) Field Descriptions (Continued) field symval Value DCMP NONE CLEAR DUND NONE CLEAR TICK NONE CLEAR NONE CLEAR 9–8 Reserved – † For CSL implementation, use the notation VP_VPIS_field_symval SPRU629 Video Port Control Registers Description Display complete.
Page 61 Video Port Control Registers Table 2–9. Video Port Interrupt Status Register (VPIS) Field Descriptions (Continued) field symval Value LFDA NONE CLEAR SFDA NONE CLEAR VINTA2 NONE CLEAR VINTA1 NONE CLEAR † For CSL implementation, use the notation VP_VPIS_field_symval 2-28 Video Port Description Long field detected on channel A interrupt detected bit.
Page 62 Table 2–9. Video Port Interrupt Status Register (VPIS) Field Descriptions (Continued) field symval Value SERRA NONE CLEAR CCMPA NONE CLEAR COVRA NONE CLEAR Reserved – † For CSL implementation, use the notation VP_VPIS_field_symval SPRU629 Video Port Control Registers Description Channel A synchronization error interrupt detected bit. BT.656 or Y/C capture mode –...
Page 63: Video Capture Port
Video Capture Port Video capture works by sampling video data on the input pins and saving it to the video port FIFO. When the amount of captured data reaches a programmed threshold level, a DMA is performed to move data from the FIFO into DSP memory.
Page 64: Video Capture Mode Selection
Video Capture Mode Selection 3.1 Video Capture Mode Selection The video capture module operates in one of nine modes as listed in Table 3–1. The transport stream interface (TSI) selection is made using the TSI bit in the video port control register (VPCTL). The CMODE bits are in the video capture channel x control register (VCxCTL).
Page 65: Bt.656 Video Capture Mode
3.2 BT.656 Video Capture Mode The BT.656 capture mode captures 8-bit or 10-bit 4:2:2 luma and chroma data multiplexed into a single data stream. Video data is conveyed in the order Cb,Y,Cr,Y,Cb,Y,Cr, etc. where the sequence Cb,Y,Cr refers to co-sited luma and chroma samples and the following Y value corresponds to the next lu- minance sample.
Page 66: Bt.656 Timing Reference Codes
BT.656 Video Capture Mode 3.2.2 BT.656 Timing Reference Codes For standard digital video, there are two reference signals, one at the begin- ning of each video data block (start of active video, SAV), and one at the end of each video block (end of active video, EAV). (Technically each line begins with the SAV code and ends just before the subsequent EAV code.) Each timing reference signal consists of a four sample sequence in the following for- mat: FF.Ch 00.0h 00.0h XY.0h.
Page 67: Bt.656 Protection Bits
Bits P0, P1, P2, and P3 have different states depending on the state of bits F, V, and H as shown in Table 3–3. Table 3–3. BT.656 Protection Bits Line Information Bits The protection bits allow the port to implement a DEDSEC (double error detec- tion, single error correction) function on the received video timing reference code.
Page 68: Bt.656 Image Window And Capture
BT.656 Video Capture Mode Table 3–4. Error Correction by Protection Bits (Continued) Received Received –P –P Bits Bits 0111 – 1000 – 1001 – 1010 – 1011 – 1100 – 1101 1110 – – 1111 – 3.2.3 BT.656 Image Window and Capture The BT.656 format is an interlaced format consisting of two fields.
Page 69: Video Capture Parameters
Figure 3–1. Video Capture Parameters Ycount=1 Ycount=1 Table 3–5 shows common digital camera standards and the number of fields per second, number of active lines per field, and the number of active pixels per line. Table 3–5. Common Video Source Parameters Number of Active Lines Video Source (Field 1/Field 2)
Page 70: Bt.656 Data Sampling
BT.656 Video Capture Mode For the BT.656 video capture mode, the FIFO buffer is divided into three sec- tions (three buffers). One section is 1280 bytes deep and is dedicated for stor- age of Y data samples. The other two sections are dedicated for storage of Cb and Cr data samples, respectively.
Page 71: Bt.656 Fifo Packing
3.2.5 BT.656 FIFO Packing Captured data is always packed into 64-bits before being written into the cap- ture FIFO(s). The packing and byte ordering is dependant upon the capture data size and the device endian mode. For little-endian operation (default), data is packed into the FIFO from right to left;...
Page 72: Bit Bt.656 Fifo Packing
BT.656 Video Capture Mode The 10-bit BT.656 mode uses three FIFOs for color separation. Two samples are packed into each word with zero or sign extension as shown in Figure 3–3. Figure 3–3. 10-Bit BT.656 FIFO Packing VCLKINA / VCLKINB VDIN[9–0] / VDIN[19–10] Cb 0 Cr 0...
Page 73: Bit Bt.656 Dense Fifo Packing
The 10-bit BT.656 dense mode uses three FIFOs for color separation. Three samples are packed into each word with zero extension to provide increased DMA bandwidth as shown in Figure 3–4. Figure 3–4. 10-Bit BT.656 Dense FIFO Packing VCLKINA / VCLKINB VDIN[9–0] / VDIN[19–10] Cb 0 Cr 0...
Page 74: Y/C Timing Reference Codes
Y/C Video Capture Mode 3.3 Y/C Video Capture Mode The Y/C capture mode is similar to the BT.656 capture mode but captures 8 or 10-bit 4:2:2 data on separate luma and chroma data streams. One data stream contains Y samples and the other stream contains multiplexed Cb and Cr samples co-sited with every other Y sample.
Page 75: Y/C Image Window And Capture
Y/C Video Capture Mode 3.3.3 Y/C Image Window and Capture The SDTV Y/C format (CCIR601) is an interlaced format consisting of two fields just like BT.656. HDTV Y/C formats may be interlaced or progressive scan. For interlaced capture, the capture windows are programmed identically to BT.656 mode.
Page 76: Y/C Fifo Packing
Y/C Video Capture Mode 3.3.4 Y/C FIFO Packing Captured data is always packed into 64 bits before being written into the capture FIFO(s). The packing and byte ordering is dependant upon the capture data size and the device endian mode. For little-endian operation (default), data is packed into the FIFO from right to left;...
Page 77: Bit Y/C Fifo Packing
The 10-bit Y/C mode uses three FIFOs for color separation. Two samples are packed into each word with zero or sign extension as shown in Figure 3–6. Figure 3–6. 10-Bit Y/C FIFO Packing VCLKINA VDIN[9–0] VDIN[19–10] Cb 0 Cr 0 Cb 1 58 57 48 47...
Page 78: Bit Y/C Dense Fifo Packing
Y/C Video Capture Mode The 10-bit Y/C dense mode uses three FIFOs for color separation. Three sam- ples are packed into each word with zero extension to provide increased DMA bandwidth as shown in Figure 3–7. Figure 3–7. 10-Bit Y/C Dense FIFO Packing VCLKINA VDIN[9–0] VDIN[19–10]...
Page 79: Bt.656 And Y/C Mode Field And Frame Operation
3.4 BT.656 and Y/C Mode Field and Frame Operation Because DMAs are used to transfer data from the capture FIFOs to memory, there is a large amount of flexibility in the way that capture fields and frames are transferred and stored in memory. In some cases, for example a DMA structure can be created to provide a set of ping-pong or round-robin memory buffers to which a continuous stream of fields are stored without DSP interven- tion.
Page 80: Bt.656 And Y/C Mode Capture Operation
BT.656 and Y/C Mode Field and Frame Operation Table 3–6. BT.656 and Y/C Mode Capture Operation VCxCTL Bit FRAME Operation Reserved Noncontinuous field 1 capture. Capture only field 1. F1C is set after field 1 capture and causes CCMPx to be set. The F1C bit must be cleared by the DSP before capture can continue.
Page 81: Vertical Synchronization
Table 3–6. BT.656 and Y/C Mode Capture Operation (Continued) VCxCTL Bit FRAME Operation Continuous field 2 capture. Capture only field 2. F2C is set after field 2 capture and causes CCMPx to be set (CCMPx interrupt can be disabled). The video port continues capturing field 2 fields, regardless of the state of F2C.
Page 82: Vertical Synchronization Programming
BT.656 and Y/C Mode Field and Frame Operation Table 3–7. Vertical Synchronization Programming VCxCTL Bit VMode VRST Vertical Counter Reset Point First EAV with V=1 after EAV with V=0 – beginning of vertical blanking period. VCOUNT increments on each EAV. First EAV with V=0 after EAV with V=1 –...
Page 83: Vcount Operation Example (Exc = 0)
Figure 3–8. VCOUNT Operation Example (EXC = 0) Line Field 1 Blanking Field 1 Active Field 2 Blanking Field 2 Active SPRU629 BT.656 and Y/C Mode Field and Frame Operation VRST=0 FINV=0 FINV=1 VCOUNT VCOUNT Field Field Video Capture Port VRST=1 FINV=0 FINV=1...
Page 84: Horizontal Synchronization
BT.656 and Y/C Mode Field and Frame Operation 3.4.3 Horizontal Synchronization Horizontal synchronization determines when the horizontal pixel/sample counter is reset. The EXC and HRST bits in VCxCTL allow you to program the event that triggers the start of a line. The encoding of these bits is shown in Table 3–8.
Page 85: Hcount Operation Example (Exc = 0)
Figure 3–9. HCOUNT Operation Example (EXC = 0) VCLKIN Blanking VDIN[9–0] Blanking Data EXC=0 HRST=0 720 721 722 723 HCOUNT EXC=0 HRST=1 HCOUNT 856 857 VCOUNT n–1 Figure 3–10. HCOUNT Operation Example (EXC = 1) VCLKIN Blanking VDIN[9–0] Blanking Data HSYNC EXC=1 HRST=0...
Page 86: Field Identification
BT.656 and Y/C Mode Field and Frame Operation 3.4.4 Field Identification In order to properly synchronize to the source data stream and capture the correct fields, field identification needs to be performed. Field identification is made using one of three methods: EAV, field indicator input, or field detect logic.
Page 87: Short And Long Field Detect
The field detect method uses HYSNC and VSYNC based field detect logic. This is used for BT.656 or Y/C systems that provide only HSYNC and VSYNC. The field detect logic samples the state of the HSYNC input on the VSYNC active edge.
Page 88: Video Input Filtering
Video Input Filtering VCTL2 is a VSYNC (vertical sync) input, then a long field is always detected. (Even if VCYSTOPn is set to the last active line, VCOUNT usually increments past VCYSTOPn + 1 while it counts the vertical front porch lines that occur prior to VSYNC active.) 3.5 Video Input Filtering The video input filter performs simple hardware scaling and resampling on...
Page 89: Chrominance Resampling Operation
3.5.2 Chrominance Resampling Operation Chrominance resampling computes chrominance values at sample points midway between the input luminance samples based on the input co-sited chrominance samples. This filter performs the horizontal portion of a conver- sion between YCbCr 4:2:2 format and YCbCr 4:2:0 format. The vertical portion of the conversion must be performed in software.
Page 90: Scaled Chrominance Resampled Filtering
Video Input Filtering Figure 3–13. 1/2 Scaled Co-Sited Filtering YCbCr 4:2:2 co-sited input samples 1/2 scaled co-sited capture results Luma (Y) Chroma (Cb/Cr) – – sample samples Figure 3–14. 1/2 Scaled Chrominance Resampled Filtering YCbCr 4:2:2 co-sited input samples 1/2 scaled chroma-resampled capture results Luma (Y)
Page 91: Edge Pixel Replication
3.5.4 Edge Pixel Replication Because the filters make use of preceding and trailing samples, filtering arti- facts can occur at the beginning of the BT.656 or Y/C active line because no samples exist before the SAV code, and at the end of the BT.656 active line because no samples exist after the EAV code.
Page 92: Capture Window Not Requiring Edge Pixel Replication
Video Input Filtering Figure 3–16 shows an example of a capture window that is smaller than the BT.656 active line. Sample a is the first sample in the horizontal capture window and sample n is the last sample. In this case, any filtering done on the first sample location uses the m leading edge captured pixels (m is 3 in this example), and any filtering done on the last sample location uses the m trailing captured pixels.
Page 93: Ancillary Data Capture
3.6 Ancillary Data Capture The BT.656 and some Y/C specifications includes provision for carrying ancillary (nonvideo) data within the horizontal and vertical blanking regions. Horizontal ancillary (HANC) data appears between the EAV code and SAV codes. Vertical ancillary (VANC) data, also called vertical blanking interval (VBI) data, appears during the active horizontal line portion of vertically blanking (for example, after an SAV with V = 1).
Page 94: Raw Data Capture Notification
Raw Data Capture Mode 3.7 Raw Data Capture Mode In the raw data capture mode, the data is sampled by the interface only when the CAPEN signal is active. Data is captured at the rate of the sender’s clock, without any interpretation or start/stop of capture based on the data values. To ensure initial capture synchronization to the beginning of a frame, an optional setup synchronization enable (SSE) bit is provided in VCxSTRT1.
Page 95: Raw Data Fifo Packing
Table 3–11. Raw Data Mode Capture Operation VCxCTL Bit FRAME Operation Noncontinuous frame capture. FRMC is set after data block capture and causes CCMPx to be set. Capture will halt upon completion of the next frame unless the FRMC bit is cleared. (DSP has the entire next frame time to clear FRMC.) Single frame capture.
Page 96: Bit Raw Data Fifo Packing
Raw Data Capture Mode The 8-bit raw-data mode stores all data in a single FIFO. Four samples are packed into each word as shown in Figure 3–17. Figure 3–17. 8-Bit Raw Data FIFO Packing VCLKINA / VCLKINB Raw 0 Raw 1 VDIN[9–2] / VDIN[19–12] 5655 4847...
Page 97: Bit Dense Raw Data Fifo Packing
The 10-bit dense raw data mode stores all data into a single FIFO. Three sam- ples are packed into each word with zero extension as shown in Figure 3–19. Figure 3–19. 10-Bit Dense Raw Data FIFO Packing VCLKOUT Raw 0 Raw 1 Raw 2 VDOUT[9–0]...
Page 98: Bit Raw Data Fifo Packing
Raw Data Capture Mode The 20-bit raw data mode stores all data into a single FIFO. One sample is placed right justified in each word and zero or sign extended as shown in Figure 3–21. Figure 3–21. 20-Bit Raw Data FIFO Packing VCLKINA VDIN[19–0] Raw 0...
Page 99: Tsi Capture Mode
3.8 TSI Capture Mode The transport stream interface (TSI) capture mode captures MPEG-2 trans- port data. 3.8.1 TSI Capture Features The video port TSI capture mode supports the following features: Supports SYNC detect using the PACSTRT input from a front-end device. Data capture at the rising edge of incoming VCLK1.
Page 100: Tsi Capture Error Detection
TSI Capture Mode Figure 3–22. Parallel TSI Capture VCLKIN CAPEN PACSTRT É É É VDIN[9:2] Sync Byte É É É Start Capture 3.8.3 TSI Capture Error Detection The video port checks for two types of errors during TSI capture. The first is a packet error on the incoming packet as indicated by an active PACERR signal.
Page 101: Program Clock Reference (Pcr) Header Format
Figure 3–23. Program Clock Reference (PCR) Header Format The video port, in conjunction with the VCXO interpolated control (VIC), allows a combined hardware and software solution to synchronize the local system time clock (STC) with the encoder time clock reference transmitted in the bit stream.
Page 102: Tsi Data Capture Notification
TSI Capture Mode The system time clock counter is initialized by software with the PCR of the first packet with a PCR header. After initialization, the counter can be reinitialized by software upon detecting a discontinuity in subsequent packet PCR header values.
Page 103: Writing To The Fifo
3.8.6 Writing to the FIFO The captured TSI packet data and the associated timestamps are written into the receive FIFO. The packet data is written first, followed by the timestamp. The FIFO controller controls both data writes and timestamp writes into the FIFO.
Page 104: Reading From The Fifo
Capture Line Boundary Conditions TSI Capture Mode / Capture Line Boundary Conditions Figure 3–27. TSI Timestamp Format (Big Endian) 56 55 PCR(7–0) PCR(15–8) PCR extension (6–0) Reserved 3.8.7 Reading from the FIFO The YSRCA location is associated with the TSI capture buffer. The YSRCA location is a read-only pseudo-register and is used to access the TSI data samples stored in the buffer.
Page 105: Capture Line Boundary Example
In Figure 3–28 (8-bit Y/C mode), the line length is not a doubleword. When the condition HCOUNT = VCXSTOP occurs, the FIFO location is written even though 8 bytes have not been received. The next capture line then begins in the next FIFO location at byte 0.
Page 106: Capturing Video In Bt.656 Or Y/C Mode
Capturing Video in BT.656 or Y/C Mode 3.10 Capturing Video in BT.656 or Y/C Mode In order to capture video in the BT.656 or Y/C format, the following steps are needed: 1) Set the last pixel to be captured in VCxSTOP1 and VCxSTOP2 (set the VCXSTOP and VCYSTOP bits).
Page 107: Handling Fifo Overrun In Bt.656 Or Y/C Mode
8) Write to VCxCTL to: Set capture mode (CMODE = 00x for BT.656 input, 10x for Y/C input). Set desired field/frame operation (CON, FRAME, CF2, CF1 bits). Set sync and field ID control (VRST, HRST, FDD, FINV, VCTL1 bits). Set 10-bit pack mode (10BPK bits), if 10-bit operation is selected. Enable scaling (SCALE and RESMPL bits), if desired and using 8-bit data.
Page 108: Capturing Video In Raw Data Mode
Capturing Video in Raw Data Mode 3.11 Capturing Video in Raw Data Mode In order to capture video in the raw data mode, the following steps are needed: 1) Set VCxSTOP1 to specify size of an image to be captured (VCXSTOP sets the lower 12 bits and VCYSTOP sets the upper 12 bits of the captured image size in pixels).
Page 109: Handling Fifo Overrun Condition In Raw Data Mode
Capturing Video in Raw Data Mode / Capturing Data in TSI Capture Mode 3.11.1 Handling FIFO Overrun Condition in Raw Data Mode In case of a FIFO overrun, the COVRx bit is set in VPIS. This condition initiates an interrupt to the DSP, if the overrun interrupt is enabled (setting the COVRx bit in VPIE enables overrun interrupt).
Page 110: Handling Fifo Overrun Condition In Tsi Capture Mode
Capturing Data in TSI Capture Mode 6) Write to TSISTCMPL, TSISTCMPM, TSISTMSKL, and TSISTMSKM if needed to initiate an interrupt, based on STC absolute time. 7) Write to TSITICKS if an interrupt is desired every x cycles of STC. 8) Write to VPCTL to select TSI capture operation (TSI = 1). 9) Write to VPIE to enable overrun (COVRA) and capture complete (CCMPA) interrupts, if desired.
Page 111: Video Capture Registers
3.13 Video Capture Registers The registers for controlling the video capture mode of operation are listed in Table 3–13. See the device-specific datasheet for the memory address of these registers. Table 3–13. Video Capture Control Registers Acronym Register Name VCASTAT Video Capture Channel A Status Register VCACTL Video Capture Channel A Control Register...
Page 112: Video Capture Channel X Status Register (Vcastat, Vcbstat)
Video Capture Registers Table 3–13. Video Capture Control Registers (Continued) Acronym Register Name TSISTCMPL TSI System Time Clock Compare LSB Register TSISTCMPM TSI System Time Clock Compare MSB Register TSISTMSKL TSI System Time Clock Compare Mask LSB Register TSISTMSKM TSI System Time Clock Compare Mask MSB Register TSITICKS TSI System Time Clock Ticks Interrupt Register 3.13.1 Video Capture Channel x Status Register (VCASTAT, VCBSTAT)
Page 113: Video Capture Channel X Status Register (Vcxstat) Field Descriptions
Table 3–14. Video Capture Channel x Status Register (VCxSTAT) Field Descriptions † † field symval Value FSYNC CLEARD FRMC NONE CAPTURED CLEAR NONE CAPTURED CLEAR NONE CAPTURED CLEAR † For CSL implementation, use the notation VP_VCxSTAT_field_symval SPRU629 Description BT.656 or Y/C Mode Raw Data Mode Current frame sync bit.
Page 114: Field Descriptions
Video Capture Registers Table 3–14. Video Capture Channel x Status Register (VCxSTAT) Field Descriptions (Continued) † † † † field field symval symval Value Value 27–16 VCYPOS OF(value) 0–FFFh Current VCOUNT 15–13 Reserved – VCFLD NONE DETECTED 11–0 VCXPOS OF(value) 0–FFFh Current HCOUNT †...
Page 115: Video Capture Channel A Control Register (Vcactl)
3.13.2 Video Capture Channel A Control Register (VCACTL) Video capture is controlled by the video capture channel A control register (VCACTL) shown in Figure 3–30 and described in Table 3–15. Figure 3–30. Video Capture Channel A Control Register (VCACTL) RSTCH BLKCAP R/WS-0 R/W-1...
Page 116: Field Descriptions
Video Capture Registers Table 3–15. Video Capture Channel A Control Register (VCACTL) Field Descriptions (Continued) † † field symval Value BLKCAP CLEAR BLOCK 29–22 Reserved – RDFE DISABLE ENABLE FINV FIELD1 FIELD2 EAVSAV EXTERN † For CSL implementation, use the notation VP_VCACTL_field_symval ‡...
Page 117: Field Descriptions
Table 3–15. Video Capture Channel A Control Register (VCACTL) Field Descriptions (Continued) † † field symval Value FLDD EAVFID VRST V1EAV V0EAV HRST VCEN DISABLE ENABLE 14–13 PK10B ZERO SIGN DENSEPK – † For CSL implementation, use the notation VP_VCACTL_field_symval ‡...
Page 118: Field Descriptions
Video Capture Registers Table 3–15. Video Capture Channel A Control Register (VCACTL) Field Descriptions (Continued) † † field symval Value LFDE DISABLE ENABLE SFDE DISABLE ENABLE RESMPL DISABLE ENABLE Reserved – SCALE NONE HALF ‡ DISABLE ENABLE † For CSL implementation, use the notation VP_VCACTL_field_symval ‡...
Page 119: Field Descriptions
Table 3–15. Video Capture Channel A Control Register (VCACTL) Field Descriptions (Continued) † † field symval Value ‡ FRAME NONE FRMCAP ‡ NONE FLDCAP ‡ NONE FLDCAP Reserved – 2–0 CMODE BT656B BT656D RAWB RAWD RAW16 RAW20 † For CSL implementation, use the notation VP_VCACTL_field_symval ‡...
Page 120: Video Capture Channel X Field 1 Start Register (Vcastrt1, Vcbstrt1)
Video Capture Registers 3.13.3 Video Capture Channel x Field 1 Start Register (VCASTRT1, VCBSTRT1) The captured image is a subset of the incoming image. The video capture channel x field 1 start register (VCASTRT1, VCBSTRT1) defines the start of the field 1 captured image. Note that the size is defined relative to incoming data (before scaling).
Page 121: Video Capture Channel X Field 1 Start Register (Vcxstrt1) Field Descriptions
Table 3–16. Video Capture Channel x Field 1 Start Register (VCxSTRT1) Field Descriptions † † field symval Value 31–28 Reserved – 27–16 VCYSTART OF(value) 0–FFFh Starting line number. DISABLE ENABLE 14–12 Reserved – 11–0 VCXSTART OF(value) 0–FFFh VCXSTART bits define VCVBLNKP †...
Page 122: Video Capture Channel X Field 1 Stop Register (Vcastop1, Vcbstop1)
Video Capture Registers 3.13.4 Video Capture Channel x Field 1 Stop Register (VCASTOP1, VCBSTOP1) The video capture channel x field 1 stop register (VCASTOP1, VCBSTOP1) defines the end of the field 1-captured image or the end of the raw data or TSI packet.
Page 123: Video Capture Channel X Field 2 Start Register (Vcastrt2, Vcbstrt2)
3.13.5 Video Capture Channel x Field 2 Start Register (VCASTRT2, VCBSTRT2) The captured image is a subset of the incoming image. The video capture channel x field 2 start register (VCASTRT2, VCBSTRT2) defines the start of the field 2 captured image. (This allows different window alignment or size for each field.) Note that the size is defined relative to incoming data (before scaling).
Page 124: Video Capture Channel X Field 2 Stop Register (Vcastop2, Vcbstop2)
Video Capture Registers 3.13.6 Video Capture Channel x Field 2 Stop Register (VCASTOP2, VCBSTOP2) The video capture channel x field 2 stop register (VCASTOP2, VCBSTOP2) defines the end of the field 2-captured image. VCxSTOP2 is shown in Figure 3–34 and described in Table 3–19. These registers are not used in raw data mode or TSI mode because their capture sizes are completely defined by the field 1 start and stop registers.
Page 125: Video Capture Channel X Vertical Interrupt Register (Vcavint, Vcbvint)
3.13.7 Video Capture Channel x Vertical Interrupt Register (VCAVINT, VCBVINT) The video capture channel x vertical interrupt register (VCAVINT, VCBVINT) controls the generation of vertical interrupts in each field. VCxVINT is shown in Figure 3–35 and described in Table 3–20. In BT.656 or Y/C mode, an interrupt can be generated upon completion of the specified line in a field (end of line when VCOUNT = VINTn).
Page 126: Video Capture Channel X Vertical Interrupt Register (Vcxvint) Field Descriptions
Video Capture Registers Table 3–20. Video Capture Channel x Vertical Interrupt Register (VCxVINT) Field Descriptions † † field symval Value VIF2 DISABLE ENABLE FSCL2 NONE FIELD2 29–28 Reserved – 27–16 VINT2 OF(value) 0–FFFh Line that vertical interrupt VIF1 DISABLE ENABLE 14–12 Reserved –...
Page 127: Video Capture Channel X Threshold Register (Vcathrld, Vcbthrld)
Video Capture Registers 3.13.8 Video Capture Channel x Threshold Register (VCATHRLD, VCBTHRLD) The video capture channel x threshold register (VCATHRLD, VCBTHRLD) determines when DMA requests are sent. VCxTHRLD is shown in Figure 3–36 and described in Table 3–21. The VCTHRLD1 bits determine when capture DMA events are generated. Once the threshold is reached, generation of further DMA events is disabled until service of the previous event(s) begins (the first FIFO read by the DMA occurs).
Page 128: Video Capture Channel X Threshold Register (Vcathrld, Vcbthrld)
Video Capture Registers Figure 3–36. Video Capture Channel x Threshold Register (VCATHRLD, VCBTHRLD) 26 25 Reserved 10 9 Reserved Legend: R = Read only; R/W = Read/Write; -n = value after reset Table 3–21. Video Capture Channel x Threshold Register (VCxTHRLD) Field Descriptions †...
Page 129: Video Capture Channel X Event Count Register (Vcaevtct, Vcbevtct)
3.13.9 Video Capture Channel x Event Count Register (VCAEVTCT, VCBEVTCT) The video capture channel x event count register (VCAEVTCT, VCBEVTCT) is programmed with the number of DMA events to be generated for each capture field. VCxEVTCT is shown in Figure 3–37 and described in Table 3–22.
Page 130: Video Capture Channel B Control Register (Vcbctl)
Video Capture Registers 3.13.10 Video Capture Channel B Control Register (VCBCTL) Video capture is controlled by the video capture channel B control register (VCBCTL) shown in Figure 3–38 and described in Table 3–23. Figure 3–38. Video Capture Channel B Control Register (VCBCTL) RSTCH BLKCAP R/WS-0...
Page 131 Table 3–23. Video Capture Channel B Control Register (VCBCTL) Field Descriptions (Continued) † † field symval Value BLKCAP CLEAR BLOCK 29–21 Reserved – FINV FIELD1 FIELD2 19–18 Reserved – VRST V1EAV V0EAV † For CSL implementation, use the notation VP_VCBCTL_field_symval ‡...
Page 132 Video Capture Registers Table 3–23. Video Capture Channel B Control Register (VCBCTL) Field Descriptions (Continued) † † field symval Value HRST VCEN DISABLE ENABLE 14–13 PK10B ZERO SIGN DENSEPK – LFDE DISABLE ENABLE SFDE DISABLE ENABLE † For CSL implementation, use the notation VP_VCBCTL_field_symval ‡...
Page 133 Table 3–23. Video Capture Channel B Control Register (VCBCTL) Field Descriptions (Continued) † † field symval Value RESMPL DISABLE ENABLE Reserved – SCALE NONE HALF ‡ DISABLE ENABLE ‡ FRAME NONE FRMCAP ‡ NONE FLDCAP † For CSL implementation, use the notation VP_VCBCTL_field_symval ‡...
Page 134: Tsi Capture Control Register (Tsictl)
Video Capture Registers Table 3–23. Video Capture Channel B Control Register (VCBCTL) Field Descriptions (Continued) † † field symval Value ‡ NONE FLDCAP 3–2 Reserved – 1–0 CMODE BT656B BT656D RAWB RAWD † For CSL implementation, use the notation VP_VCBCTL_field_symval ‡...
Page 135: Tsi Capture Control Register (Tsictl) Field Descriptions
Table 3–24. TSI Capture Control Register (TSICTL) Field Descriptions † † field symval Value 31–6 Reserved – ENSTC HALTED CLKED TCKEN DISABLE STEN DISABLE CTMODE 90KHZ STCLK ERRFILT ACCEPT REJECT Reserved – † For CSL implementation, use the notation VP_TSICTL_field_symval SPRU629 Description BT.656, Y/C Mode,...
Page 136: Tsi Clock Initialization Lsb Register (Tsiclkinitl)
Video Capture Registers 3.13.12 TSI Clock Initialization LSB Register (TSICLKINITL) The transport stream interface clock initialization LSB register (TSICLKINITL) is used to initialize the hardware counter to synchronize with the system time clock. TSICLKINITL is shown in Figure 3–40 and described in Table 3–25. On receiving the first packet containing a program clock reference (PCR) and the PCR extension value, the DSP writes the 32 least-significant bits (LSBs) of the PCR into TSICLKINITL.
Page 137: Tsi Clock Initialization Msb Register (Tsiclkinitm)
3.13.13 TSI Clock Initialization MSB Register (TSICLKINITM) The transport stream interface clock initialization MSB register (TSICLKINITM) is used to initialize the hardware counter to synchronize with the system time clock. TSICLKINITM is shown in Figure 3–41 and described in Table 3–26. On receiving the first packet containing a program clock reference (PCR) header, the DSP writes the most-significant bit (MSB) of the PCR and the 9-bit PCR extension into TSICLKINITM.
Page 138: Tsi System Time Clock Lsb Register (Tsistclkl)
Video Capture Registers 3.13.14 TSI System Time Clock LSB Register (TSISTCLKL) The transport stream interface system time clock LSB register (TSISTCLKL) contains the 32 least-significant bits (LSBs) of the program clock reference (PCR). The system time clock value is obtained by reading TSISTCLKL and TSISTCLKM.
Page 139: Tsi System Time Clock Msb Register (Tsistclkm)
3.13.15 TSI System Time Clock MSB Register (TSISTCLKM) The transport stream interface system time clock MSB register (TSISTCLKM) contains the most-significant bit (MSB) of the program clock reference (PCR) and the 9 bits of the PCR extension. The system time clock value is obtained by reading TSISTCLKM and TSISTCLKL.
Page 140: Tsi System Time Clock Compare Lsb Register (Tsistcmpl)
Video Capture Registers 3.13.16 TSI System Time Clock Compare LSB Register (TSISTCMPL) The transport stream interface system time clock compare LSB register (TSISTCMPL) is used to generate an interrupt at some absolute time based on the STC. TSISTCMPL holds the 32 least-significant bits (LSBs) of the absolute time compare (ATC).
Page 141: Tsi System Time Clock Compare Msb Register (Tsistcmpm) Field Descriptions
3.13.17 TSI System Time Clock Compare MSB Register (TSISTCMPM) The transport stream interface system time clock compare MSB register (TSISTCMPM) is used to generate an interrupt at some absolute time based on the STC. TSISTCMPM holds the most-significant bit (MSB) of the absolute time compare (ATC).
Page 142: Tsi System Time Clock Compare Mask Lsb Register (Tsistmskl)
Video Capture Registers 3.13.18 TSI System Time Clock Compare Mask LSB Register (TSISTMSKL) The transport stream interface system time clock compare mask LSB register (TSISTMSKL) holds the 32 least-significant bits (LSBs) of the absolute time compare mask (ATCM). This value is used with TSISTMSKM to mask out bits during the comparison of the ATC to the system time clock for absolute time.
Page 143: Tsi System Time Clock Compare Mask Msb Register (Tsistmskm)
3.13.19 TSI System Time Clock Compare Mask MSB Register (TSISTMSKM) The transport stream interface system time clock compare mask MSB register (TSISTMSKM) holds the most-significant bit (MSB) of the absolute time compare mask (ATCM). This value is used with TSISTMSKL to mask out bits during the comparison of the ATC to the system time clock for absolute time.
Page 144: Tsi System Time Clock Ticks Interrupt Register (Tsiticks)
Video Capture Registers 3.13.20 TSI System Time Clock Ticks Interrupt Register (TSITICKS) The transport stream interface system time clock ticks interrupt register (TSITICKS) is used to generate an interrupt after a certain number of ticks of the 27-MHz system time clock. When the TICKCT value is set to X and the TCKEN bit in TSICTL is set, the TICK bit in VPIS is set every X + 1 STCLK cycles.
Page 145: Video Capture Fifo Registers
3.14 Video Capture FIFO Registers The capture FIFO mapping registers are listed in Table 3–34. These registers provide read access to the capture FIFOs. These pseudo-registers should be mapped into DSP memory space rather than configuration register space in order to provide high-speed access. See the device-specific datasheet for the memory address of these registers.
Page 146: Video Display Port
The video port peripheral can operate as a video capture port, video display port, or transport stream interface (TSI) capture port. This chapter discusses the video display port. Topic Video Display Mode Selection ........BT.656 Video Display Mode .
Page 147: Video Display Mode Selection
Video Display Mode Selection 4.1 Video Display Mode Selection The video display module operates in one of three modes as listed in Table 4–1. The DMODE bits are in the video display control register (VDCTL). The Y/C and 16/20-bit raw display modes may only be selected if the DCDIS bit in the video port control register (VPCTL) is cleared to 0.
Page 148: Ntsc Compatible Interlaced Display
Figure 4–1. NTSC Compatible Interlaced Display Field 1 Line 20 Line 21 Line 22 Line 261 Line 262 Line 263 Figure 4–2. SMPTE 296M Compatible Progressive Scan Display Field 1 Line 26 Line 27 Line 28 Line 29 Line 30 Line 741 Line 742 Line 743...
Page 149: Interlaced Blanking Intervals And Video Areas
Video Display Mode Selection Figure 4–3. Interlaced Blanking Intervals and Video Areas Field 1 Vertical Blanking Field 2 Vertical Blanking Video Display Port Field 1 Image Vertical Offset Field 1 Active Video Field 1 Image Width Field 2 Image Vertical Offset Field 2 Active Video Field 2 Image Width SPRU629...
Page 150: Video Display Counters
Figure 4–4. Progressive Blanking Intervals and Video Area Field 1 Vertical Blanking 4.1.2 Video Display Counters To generate the image timing, the video display module uses five counters: Frame line counter (FLCOUNT) Frame pixel counter (FPCOUNT) Image line counter (ILCOUNT) Image pixel counter (IPCOUNT) Video clock counter (VCCOUNT) The frame line counter (FLCOUNT) counts the total number of lines per frame...
Page 151: Horizontal Blanking And Horizontal Sync Timing
Video Display Mode Selection The image line counter (ILCOUNT) and the image pixel counter (IPCOUNT) track the visible image within the field. ILCOUNT begins counting at the first display image line in each field. IPCOUNT begins counting at the first dis- played image pixel on each line.
Page 152: Sync Signal Generation
Note that the signals can transition at any place along the video line (specified by the XSTART and XSTOP bits of the appropriate registers). In this case, VBLNK starts at horizontal count VBLNKXSTART2 = 429 on scan line VBLNKYSTART2 = 263 (565/60 operation). Figure 4–6.
Page 153: External Sync Operation
Video Display Mode Selection 4.1.4 External Sync Operation The video display module may be synchronized with an external video source using external sync signals. VCTL1 may be configured as an external horizon- tal sync input. When the external HSYNC is asserted, FPCOUNT is loaded with the HRLD value and VCCOUNT is loaded with the CRLD value.
Page 154: Bt.656 Video Display Mode
4.2 BT.656 Video Display Mode The BT.656 display mode outputs 8-bit or 10-bit 4:2:2 co-sited luma and chroma data multiplexed into a single data stream. Pixels are output in pairs with each pair consisting of two luma samples and two chroma samples. The chroma samples are associated with the first luma pixel of the pair.
Page 155: Bt.656 Horizontal Blanking Timing
BT.656 Video Display Mode Figure 4–10. 625/50 BT.656 Horizontal Blanking Timing 720 721 722 723 FPCOUNT VCLKOUT Blanking VDOUT[9–0] Blanking Data SAV and EAV codes are identified by a 3-byte preamble of FFh, 00h, and 00h. This combination must be avoided in the video data output by the video port to prevent accidental generation of an invalid sync code.
Page 156: Digital Vertical F And V Transitions
Figure 4–11.Digital Vertical F and V Transitions 525 lines/60 Hz Line 4 Blanking Optional blanking Field 1 (F = 0) Image: Field 1 Line 266 Blanking Optional blanking Field 2 (F = 1) Image: Field 2 Line 3 H = 0 (SAV) H = 1 (EAV) LIne Number (EAV)
Page 157: Blanking Codes
BT.656 Video Display Mode 4.2.2 Blanking Codes The time between the EAV and SAV code on each line represents the horizontal blanking interval. During this time, the video port outputs digital video blanking values. These values are 10.0h for luma (Y) samples and 80.0h for chroma (Cb/Cr) samples.
Page 158: Bit Bt.656 Fifo Unpacking
4.2.4 BT.656 FIFO Unpacking Display data is always packed into the FIFOs in 64-bit words and must be unpacked before being sent to the video display data pipeline. The unpacking and byte ordering is dependant upon the display data size and the device endian mode.
Page 159: Bit Bt.656 Fifo Unpacking
BT.656 Video Display Mode For 10-bit BT.656 operation, two samples are unpacked from each word as shown in Figure 4–13. Figure 4–13. 10-Bit BT.656 FIFO Unpacking VCLKOUT VDOUT[9–0] Cb 0 Cr 0 58 57 48 47 Y 15 Y 11 Y FIFO 58 57 48 47...
Page 160: Bt.656 Dense Fifo Unpacking
In 10-bit BT.656 dense-pack mode, three samples are unpacked from each word in the FIFO as seen in Figure 4–14. Figure 4–14. BT.656 Dense FIFO Unpacking VCLKOUT VDOUT[9–0] Cb 0 Cr 0 63 61 5251 Y 23 Y 22 Y 17 Y 16 Y 11 Y 10...
Page 161: Y/C Video Display Mode
Y/C Video Display Mode 4.3 Y/C Video Display Mode The Y/C display mode is similar to the BT.656 display mode but outputs 8 or 10-bit data on separate luma and chroma data streams. One data stream contains Y samples and the other stream contains multiplexed Cb and Cr samples co-sited with every other luminance sample.
Page 162: Y/C Blanking Codes
4.3.2 Y/C Blanking Codes The time between the EAV and SAV code on each line represents the horizon- tal blanking interval. During this time, the video port outputs the digital video blanking values. These values are 10.0h for luma (Y) samples and 80.0h for chroma (Cb/Cr) samples.
Page 163: Bit Y/C Fifo Unpacking
Y/C Video Display Mode The 8-bit Y/C mode uses three FIFOs for color separation. Four samples are unpacked from each word as shown in Figure 4–16. Figure 4–16. 8-Bit Y/C FIFO Unpacking VCLKOUT VDOUT[9–2] VDOUT[19–12] Cb 0 Cr 0 5655 4847 Y 31 Y 30...
Page 164: Bit Y/C Fifo Unpacking
For 10-bit operation, two samples are unpacked from each FIFO word. This is shown in Figure 4–17. Figure 4–17. 10-Bit Y/C FIFO Unpacking VCLKOUT VDOUT[9–0] VDOUT[19–10] Cb 0 Cr 0 Cb 1 5857 4847 Y 15 Y 11 Y FIFO 5857 4847 Cb 7...
Page 165: Bit Y/C Dense Fifo Unpacking
Y/C Video Display Mode In 10-bit Y/C dense-pack mode, three samples are unpacked from each word in the FIFO as seen in Figure 4–18. Figure 4–18. 10-Bit Y/C Dense FIFO Unpacking VCLKOUT VDOUT[9–0] VDOUT[19–10] Cb 0 Cr 0 Cb 1 63 61 5251 Y 23...
Page 166: Video Output Filtering
4.4 Video Output Filtering The video output filter performs simple hardware scaling and resampling on outgoing 8-bit BT.656 or 8-bit Y/C data. Filtering hardware is disabled during 10-bit or raw data display modes. 4.4.1 Output Filter Modes The output filter has four modes of operation: no-filtering, 2 scaling, chromi- nance resampling, and 2 scaling with chrominance resampling.
Page 167: Chrominance Resampling Operation
Video Output Filtering 4.4.2 Chrominance Resampling Operation Chrominance resampling computes chrominance values at sample points corresponding to output luminance samples based on the input interspersed chrominance samples. This filter performs the conversion between inter- spersed YCbCr 4:2:2 format and co-sited YCbCr 4:2:2 format. The vertical portion of the conversion from YCbCr 4:2:0 to interspersed YCbCr 4:2:2 must be performed in software.
Page 168: Edge Pixel Replication
Figure 4–20. 2x Co-Sited Scaling YCbCr 4:2:2 co–sited source pixels a’ 2 upscaled output Y’ b = Y b Cb’ c = Cb c Cr’ c = Cr c Luma (Y) – – sample Figure 4–21. 2x Interspersed Scaling YCbCr 4:2:2 interspersed source pixels 2x upscaled...
Page 169: Interspersed Chroma Edge Replication
Video Output Filtering Examples of luma edge and chroma edge replication for 2 interspersed to co-sited output are shown in Figure 4–23 and Figure 4–24, respectively. Figure 4–23. Luma Edge Replication a’ Leading edge replicated luma Y’ a = Y a Y’...
Page 170: Ancillary Data Display
4.5 Ancillary Data Display The following sections discuss ancillary data display. No special previsions are made for the display of horizontal ancillary (HANC) or vertical ancillary (VANC), also called vertical blanking interval (VBI), data. 4.5.1 Horizontal Ancillary (HANC) Data Display HANC data can be displayed using the normal video display mechanism by programming IMGHSIZEn to occur prior to the SAV code.
Page 171: Raw Mode Rgb Output Support
Raw Data Display Mode 4.6.1 Raw Mode RGB Output Support The raw data display mode has a special pixel count feature that allows the FPCOUNT increment rate to be set. FPCOUNT increments only when INCPIX samples have been sent out. This option allows proper tracking of the display pixels when sending out sequential RGB samples.
Page 172: Bit Raw Dense Fifo Unpacking
For 10-bit operation, two samples are unpacked from each FIFO word. This is shown in Figure 4–26. Figure 4–26. 10-Bit Raw FIFO Unpacking VCLKOUT VDOUT[9–0] Raw 0 Raw 1 Raw 2 5857 4847 Raw 15 Raw 11 Raw 7 Raw 3 Y FIFO 5857 4847...
Page 173: Bit Raw Fifo Unpacking
Raw Data Display Mode Figure 4–28 shows the 16-bit raw mode. Two samples are unpacked from each word of the FIFO. Figure 4–28. 16-Bit Raw FIFO Unpacking VCLKOUT VDOUT[19–12]/VDOUT[9–2] Raw 0 Raw 1 4847 Raw 11 Raw 7 Raw 3 Raw FIFO 4847 Raw 8...
Page 174: Bit Raw 3/4 Fifo Unpacking
In 8-bit raw ¾ mode, three samples are unpacked from the FIFO and the remaining byte is ignored. This is shown in Figure 4–30. Figure 4–30. 8-Bit Raw 3/4 FIFO Unpacking VCLKOUT Raw 0 Raw 1 VDOUT[9–2] (R0) (G0) 5655 4847 Raw 11 (B3) Raw 10 (G3)
Page 175: Video Display Field And Frame Operation
Video Display Field and Frame Operation 4.7 Video Display Field and Frame Operation As a video source, the video port always outputs entire frames of data and transmits continuous video control signals. Depending on the DMA structure, however, the video port may need to interrupt the DSP on a field or frame basis to allow it to update video port registers or DMA parameters.
Page 176 Table 4–4. Display Operation VDCTL Bit FRAME Operation Reserved Noncontinuous field 1 display. Display only field 1. F1D is set after field 1 display and causes DCMPx to be set. The F1D bit must be cleared by the DSP or a DCNA interrupt occurs. (The DSP has the en- tire field 2 time to clear F1D before next field 1 begins.) Can also be used for single progressive frame display (internal timing codes only).
Page 177: Video Display Event Generation
Video Display Field and Frame Operation Table 4–4. Display Operation (Continued) VDCTL Bit FRAME Operation Continuous field 2 display. Display only field 2. F2D is set after field 2 display and causes DCMPx to be set (DCMPx interrupt can be dis- abled).
Page 178: Display Line Boundary Conditions
Display Line Boundary Conditions 4.8 Display Line Boundary Conditions In order to simplify DMA transfers, FIFO doublewords do not contain data from more than one display line. This means that a FIFO read must be performed whenever 8-bytes have been output or when the line complete condition (IPCOUNT = IMGHSIZE) occurs.
Page 179: Display Line Boundary Example
Display Line Boundary Conditions Figure 4–32. Display Line Boundary Example Line n VCLKOUT Y 72 Y 74 VDOUT[9–2] Cb 36 Cr 36 Cb 37 VDOUT[19–12] 5655 4847 Y 77 Y 71 Y 70 Y 69 Y FIFO 5655 4847 Cb 7 Cb 6 Cb 5 Cb 38...
Page 180: Display Timing Examples
4.9 Display Timing Examples The following are examples of display output for several modes of operation. 4.9.1 Interlaced BT.656 Timing Example This section shows an example of BT.656 display output for a 704 408 inter- laced output image as might be generated by MPEG decoding. The horizontal output timing is shown in Figure 4–33.
Page 181: Bt.656 Interlaced Display Horizontal Timing Example
Figure 4–33. BT.656 Interlaced Display Horizontal Timing Example VCLKIN FPCOUNT 720 721 722 723 735 736 IPCOUNT 703 703 703 703 703 703 VCTL1 (HBLNK )† § VCTL1 (HSYNC) † § VCLKOUT VDOUT[9–0] EAV Blanking Data FLCOUNT n – 1 FRMWIDTH = 858 IMGHOFF1 = 8 HSYNCSTART = 736...
Page 182 Display Timing Examples The interlaced BT.656 vertical output timing is shown in Figure 4–34. The BT.656 active field 1 is 244-lines high and active field 2 is 243-lines high. This example shows the 480-line image window centered in the screen. This results in an IMGVOFFn of 3 lines and also results in a nondata line at the end of field 1 due to its extra active line.
Page 183: Bt.656 Interlaced Display Vertical Timing Example
Display Timing Examples Figure 4–34. BT.656 Interlaced Display Vertical Timing Example FLCOUNT Field 1 Blanking É É É É É É É Field 1 Active É É É É É É É Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Field 1 Image Ç...
Page 184: Interlaced Raw Display Example
Display Timing Examples 4.9.2 Interlaced Raw Display Example This section shows an example of raw display output for the same 704 interlaced image. The horizontal output timing is shown in Figure 4–35. This diagram assumes that there is a two VCLK pipeline delay between the internal counter changing and the output on external pins.
Page 185: Raw Interlaced Display Horizontal Timing Example
Figure 4–35. Raw Interlaced Display Horizontal Timing Example VCLKIN FPCOUNT IPCOUNT VCTL1 (HBLNK) † § VCTL1 (HSYNC) † § VCLKOUT Blanking É É VDOUT[19–0] § É É É É FLCOUNT n – 1 FRMWIDTH = 858 IMGHOFF1 = 8 HSYNCSTART = 736 HBLNKSTART = 720 IMGHSIZE1 = 704 HSYNCSTOP = 800...
Page 186 Display Timing Examples The vertical output timing for raw mode is shown in Figure 4–36. This example outputs the same 480-line window. Note that the raw display mode is typically noninterlaced for output to a monitor. This example shows the more complex interlaced case.
Page 187: Raw Interlaced Display Vertical Timing Example
Display Timing Examples Figure 4–36. Raw Interlaced Display Vertical Timing Example FLCOUNT Field 1 Blanking Ç Ç Ç Ç Ç Ç Ç Ç Field 1 Active É É É É É É É É Ç Ç Ç Ç Ç Ç Ç Ç É...
Page 188: Y/C Progressive Display Example
Display Timing Examples 4.9.3 Y/C Progressive Display Example This section shows an example of progressive display operation. The output format follows SMPTE 296M-2001 specifications for a 1280 720/60 system. The example is for a 1264 716 progressive output image. The horizontal output timing is shown in Figure 4–37. This diagram assumes that there is a two VCLK pipeline delay between the internal counter changing and the output on external pins.
Page 189: Y/C Progressive Display Horizontal Timing Example
Figure 4–37. Y/C Progressive Display Horizontal Timing Example VCLKIN FPCOUNT IPCOUNT VCTL1 (HBLNK) † § VCTL1 (HSYNC) † § VCLKOUT Blanking VDOUT[9–0] § VDOUT[19–0] § Blanking Data FLCOUNT n – 1 FRMWIDTH = 1650 IMGHOFF1 = 8 HSYNCSTART = 1350 HBLNKSTART = 1280 IMGHSIZE1 = 1264 HSYNCSTOP = 1430...
Page 190 Display Timing Examples The vertical output timing is shown in Figure 4–38. SMPTE 296M has a single active field 1 that is 720-lines high. This example shows the 716-line image window with an IMGVOFFn of 3 lines and also results in a nondata line at the end of the field.
Page 191: Y/C Progressive Display Vertical Timing Example
Display Timing Examples Figure 4–38. Y/C Progressive Display Vertical Timing Example FLCOUNT Field 1 Blanking Ç Ç Ç Ç Ç Ç Ç Field 1 Active Ç Ç Ç Ç Ç Ç Ç É É É É É É É É É É É É É É Field 1 Image É...
Page 192: Displaying Video In Bt.656 Or Y/C Mode
4.10 Displaying Video in BT.656 or Y/C Mode In order to display video in the BT.656 or Y/C format, the following steps are needed: 1) Set the frame size in VDFRMSZ. Set the number of lines per frame (FRMHIGHT) and the number of pixels per line (FRMWIDTH). 2) Set the horizontal blanking in VDHBLNK.
Page 193 Displaying Video in BT.656 or Y/C Mode 12) Configure a DMA to move data from the Y buffer in the DSP memory to YDSTA (memory-mapped Y display FIFO). The transfers should be triggered by the YEVT. 13) Configure a DMA to move data from the Cb buffer in the DSP memory to CBDST (memory-mapped Cb display FIFO).
Page 194: Displaying Video In Raw Data Mode
22) If continuous display is enabled, the video port begins displaying again at the start of the next field or frame. If noncontinuous field 1 and field 2 or frame display is enabled, the next field or frame is displayed, during which the DSP must clear the appropriate completion status bit or a DCNA interrupt occurs and incorrect data may be output.
Page 195 Displaying Video in Raw Data Mode 11) Set the horizontal synchronization in VDHSYNC. Specify the frame pixel counter value for a pixel where HSYNC gets asserted (HSYNCYSTART) and width of the HSYNC pulse (HSYNCSTOP) in frame pixel clocks. 12) Set the video display field 1 timing. Specify the first line and pixel of field 1 in VDFLDT1.
Page 196: Handling Underrun Condition Of The Display Fifo
22) If continuous display is enabled, the video port begins displaying again at the start of the next field or frame. If noncontinuous field 1 and field 2 or frame display is enabled, the next field or frame is displayed, during which the DSP must clear the appropriate completion status bit or a DCNA interrupt occurs and incorrect data may be output.
Page 197: Video Display Registers
Video Display Registers 4.12 Video Display Registers The registers for controlling the video display mode of operation are listed in Table 4–5. See the device-specific datasheet for the memory address of these registers. Table 4–5. Video Display Control Registers Acronym Register Name VDSTAT Video Display Status Register...
Page 198: Video Display Status Register (Vdstat)
Table 4–5. Video Display Control Registers (Continued) Acronym Register Name VDDEFVAL Video Display Default Display Value Register VDVINT Video Display Vertical Interrupt Register VDFBIT Video Display Field Bit Register VDVBIT1 Video Display Field 1 Vertical Blanking Bit Register VDVBIT2 Video Display Field 2 Vertical Blanking Bit Register 4.12.1 Video Display Status Register (VDSTAT) The video display status register (VDSTAT) indicates the current display status of the video port.
Page 199: Video Display Status Register (Vdstat) Field Descriptions
Video Display Registers Table 4–6. Video Display Status Register (VDSTAT) Field Descriptions † † field symval Value Reserved – FRMD NONE DISPLAYED NONE DISPLAYED NONE DISPLAYED 27–16 VDYPOS OF(value) 0–FFFh Current frame line counter (FLCOUNT) value. Index of the 15–14 Reserved –...
Page 200: Video Display Control Register (Vdctl)
4.12.2 Video Display Control Register (VDCTL) The video display is controlled by the video display control register (VDCTL). The VDCTL is shown in Figure 4–40 and described in Table 4–7. Figure 4–40. Video Display Control Register (VDCTL) RSTCH BLKDIS Reserved R/WS-0 R/W-1 R/W-0...
Page 201 Video Display Registers Table 4–7. Video Display Control Register (VDCTL) Field Descriptions (Continued) † † † † field field symval symval Value Value BLKDIS CLEAR BLOCK Reserved – PVPSYN DISABLE ENABLE 27–24 Reserved – OUTPUT FSINPUT OUTPUT VSINPUT † For CSL implementation, use the notation VP_VDCTL_field_symval ‡...
Page 202 Table 4–7. Video Display Control Register (VDCTL) Field Descriptions (Continued) † † † † field field symval symval Value Value OUTPUT HSINPUT VCTL3S CBLNK 19–18 VCTL2S VYSYNC VBLNK CSYNC 17–16 VCTL1S HYSYNC HBLNK AVID VDEN DISABLE ENABLE N10UNPK D10UNPK † For CSL implementation, use the notation VP_VDCTL_field_symval ‡...
Page 203 Video Display Registers Table 4–7. Video Display Control Register (VDCTL) Field Descriptions (Continued) † † † † field field symval symval Value Value RGBX DISABLE ENABLE RSYNC DISABLE ENABLE DVEN BLANKING RESMPL DISABLE ENABLE Reserved – SCALE NONE ‡ DISABLE ENABLE †...
Page 204 Table 4–7. Video Display Control Register (VDCTL) Field Descriptions (Continued) † † † † field field symval symval Value Value ‡ FRAME NONE FRMDIS ‡ NONE FLDDIS ‡ NONE FLDDIS Reserved – 2–0 DMODE BT656B BT656D RAWB RAWD YC16 YC20 RAW16 RAW20 †...
Page 205: Video Display Frame Size Register (Vdfrmsz)
Video Display Registers 4.12.3 Video Display Frame Size Register (VDFRMSZ) The video display frame size register (VDFRMSZ) sets the display channel frame size by setting the ending values for the frame line counter (FLCOUNT) and the frame pixel counter (FPCOUNT). The VDFRMSZ is shown in Figure 4–41 and described in Table 4–8.
Page 206: Video Display Horizontal Blanking Register (Vdhblnk)
4.12.4 Video Display Horizontal Blanking Register (VDHBLNK) The video display horizontal blanking register (VDHBLNK) controls the display horizontal blanking. The VDHBLNK is shown in Figure 4–42 and described in Table 4–9. Every time the frame pixel counter (FPCOUNT) is equal to HBLNKSTART, HBLNK is asserted.
Page 207: Video Display Field 1 Vertical Blanking Start Register (Vdvblks1)
Video Display Registers Table 4–9. Video Display Horizontal Blanking Register (VDHBLNK) Field Descriptions † † field symval 31–28 Reserved – 27–16 HBLNKSTOP OF(value) HBDLA NONE DELAY 14–12 Reserved – 11–0 HBLNKSTART OF(value) † For CSL implementation, use the notation VP_VDHBLNK_field_symval 4.12.5 Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1) The video display field 1 vertical blanking start register (VDVBLKS1) controls the start of vertical blanking in field 1.
Page 208: Video Display Field 1 Vertical Blanking Start Register (Vdvblks1)
Figure 4–43. Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1) 28 27 Reserved 12 11 Reserved Legend: R = Read only; R/W = Read/Write; -n = value after reset Table 4–10. Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1) Field Descriptions †...
Page 209: Video Display Field 1 Vertical Blanking End Register (Vdvblke1)
Video Display Registers 4.12.6 Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) The video display field 1 vertical blanking end register (VDVBLKE1) controls the end of vertical blanking in field 1. The VDVBLKE1 is shown in Figure 4–44 and described in Table 4–11. In raw data mode, VBLNK is deasserted whenever the frame line counter (FLCOUNT) is equal to VBLNKYSTOP1 and the frame pixel counter (FPCOUNT) is equal to VBLNKXSTOP1 (this is shown in Figure 4–6, page 4-7).
Page 210: Video Display Field 1 Vertical Blanking End Register (Vdvblke1)
Table 4–11. Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) Field Descriptions † † field symval 31–28 Reserved – 27–16 VBLNKYSTOP1 OF(value) 15–12 Reserved – 11–0 VBLNKXSTOP1 OF(value) † For CSL implementation, use the notation VP_VDVBLKE1_field_symval 4.12.7 Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) The video display field 2 vertical blanking start register (VDVBLKS2) controls the start of vertical blanking in field 2.
Page 211: Video Display Field 2 Vertical Blanking Start Register (Vdvblks2)
Video Display Registers Figure 4–45. Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) 28 27 Reserved 12 11 Reserved Legend: R = Read only; R/W = Read/Write; -n = value after reset Table 4–12. Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) Field Descriptions †...
Page 212: Video Display Field 2 Vertical Blanking End Register (Vdvblke2)
4.12.8 Video Display Field 2 Vertical Blanking End Register (VDVBLKE2) The video display field 2 vertical blanking end register (VDVBLKE2) controls the end of vertical blanking in field 2. The VDVBLKE2 is shown in Figure 4–46 and described in Table 4–13. In raw data mode, VBLNK is deasserted whenever the frame line counter (FLCOUNT) is equal to VBLNKYSTOP2 and the frame pixel counter (FPCOUNT) is equal to VBLNKXSTOP2 (this is shown in Figure 4–6, page 4-7).
Page 213: Video Display Field 1 Image Offset Register (Vdimgoff1)
Video Display Registers Table 4–13. Video Display Field 2 Vertical Blanking End Register (VDVBLKE2) Field Descriptions † † field symval 31–28 Reserved – 27–16 VBLNKYSTOP2 OF(value) 15–12 Reserved – 11–0 VBLNKXSTOP2 OF(value) † For CSL implementation, use the notation VP_VDVBLKE2_field_symval 4.12.9 Video Display Field 1 Image Offset Register (VDIMGOFF1) The video display field 1 image offset register (VDIMGOFF1) defines the field 1 image offset and specifies the starting location of the displayed image...
Page 214: Video Display Field 1 Image Offset Register (Vdimgoff1)
Figure 4–47. Video Display Field 1 Image Offset Register (VDIMGOFF1) 28 27 Reserved R/W-0 12 11 Reserved R/W-0 Legend: R = Read only; R/W = Read/Write; -n = value after reset Table 4–14. Video Display Field 1 Image Offset Register (VDIMGOFF1) Field Descriptions †...
Page 215: Video Display Field 1 Image Size Register (Vdimgsz1)
Video Display Registers 4.12.10 Video Display Field 1 Image Size Register (VDIMGSZ1) The video display field 1 image size register (VDIMGSZ1) defines the field 1 image area and specifies the size of the displayed image within the active dis- play. The VDIMGSZ1 is shown in Figure 4–48 and described in Table 4–15. The image pixel counter (IPCOUNT) counts displayed image pixel output on each of the displayed image.
Page 216: Video Display Field 2 Image Offset Register (Vdimgoff2)
4.12.11 Video Display Field 2 Image Offset Register (VDIMGOFF2) The video display field 2 image offset register (VDIMGOFF2) defines the field 2 image offset and specifies the starting location of the displayed image relative to the start of the active display. The VDIMGOFF2 is shown in Figure 4–49 and described in Table 4–16.
Page 217: Video Display Field 2 Image Offset Register (Vdimgoff2) Field Descriptions
Video Display Registers Table 4–16. Video Display Field 2 Image Offset Register (VDIMGOFF2) Field Descriptions † † field symval NONE NEGOFF 30–28 Reserved – 27–16 IMGVOFF2 OF(value) 0–FFFh NONE NEGOFF 14–12 Reserved – 11–0 IMGHOFF2 OF(value) 0–FFFh † For CSL implementation, use the notation VP_VDIMGOFF2_field_symval 4-72 Video Display Port Description...
Page 218: Video Display Field 2 Image Size Register (Vdimgsz2)
4.12.12 Video Display Field 2 Image Size Register (VDIMGSZ2) The video display field 2 image size register (VDIMGSZ2) defines the field 2 image area and specifies the size of the displayed image within the active dis- play. The VDIMGSZ2 is shown in Figure 4–50 and described in Table 4–17. The image pixel counter (IPCOUNT) counts displayed image pixel output on each of the displayed image.
Page 219: Video Display Field 1 Timing Register (Vdfldt1)
Video Display Registers 4.12.13 Video Display Field 1 Timing Register (VDFLDT1) The video display field 1 timing register (VDFLDT1) sets the timing of the field identification signal. The VDFLDT1 is shown in Figure 4–51 and described in Table 4–18. In raw data mode, the FLD signal is deasserted to indicate field 1 display whenever the frame line counter (FLCOUNT) is equal to FLD1YSTART and the frame pixel counter (FPCOUNT) is equal to FLD1XSTART (this is shown in Figure 4–6, page 4-7).
Page 220: Video Display Field 2 Timing Register (Vdfldt2)
4.12.14 Video Display Field 2 Timing Register (VDFLDT2) The video display field 2 timing register (VDFLDT2) sets the timing of the field identification signal. The VDFLDT2 is shown in Figure 4–52 and described in Table 4–19. In raw data mode, the FLD signal is asserted whenever the frame line counter (FLCOUNT) is equal to FLD2YSTART and the frame pixel counter (FPCOUNT) is equal to FLD2XSTART (this is shown in Figure 4–6, page 4-7).
Page 221: Video Display Threshold Register (Vdthrld)
Video Display Registers 4.12.15 Video Display Threshold Register (VDTHRLD) The video display threshold register (VDTHRLD) sets the display FIFO thresh- old to determine when to load more display data. The VDTHRLD is shown in Figure 4–53 and described in Table 4–20. The VDTHRLDn bits determines how much space must be available in the display FIFOs before the appropriate DMA event may be generated.
Page 222: Video Display Threshold Register (Vdthrld) Field Descriptions
Table 4–20. Video Display Threshold Register (VDTHRLD) Field Descriptions † † field symval 31–26 Reserved – 25–16 VDTHRLD2 OF(value) 0–3FFh 15–12 INCPIX OF(value) 11–10 Reserved – 9–0 VDTHRLD1 OF(value) 0–3FFh † For CSL implementation, use the notation VP_VDTHRLD_field_symval SPRU629 Description BT.656 and Y/C Mode Value Reserved.
Page 223: Video Display Horizontal Synchronization Register (Vdhsync)
Video Display Registers 4.12.16 Video Display Horizontal Synchronization Register (VDHSYNC) The video display horizontal synchronization register (VDHSYNC) controls the timing of the horizontal synchronization signal. The VDHSYNC is shown in Figure 4–54 and described in Table 4–21. Generation of the horizontal synchronization is shown in Figure 4–5, page 4-6.
Page 224: Video Display Field 1 Vertical Synchronization Start Register (Vdvsyns1)
4.12.17 Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1) The video display field 1 vertical synchronization start register (VDVSYNS1) controls the start of vertical synchronization in field 1. The VDVSYNS1 is shown in Figure 4–55 and described in Table 4–22. Generation of the vertical synchronization is shown in Figure 4–6, page 4-7.
Page 225: Video Display Field 1 Vertical Synchronization End Register (Vdvsyne1)
Video Display Registers 4.12.18 Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1) The video display field 1 vertical synchronization end register (VDVSYNE1) controls the end of vertical synchronization in field 1. The VDVSYNE1 is shown in Figure 4–56 and described in Table 4–23. Generation of the vertical synchronization is shown in Figure 4–6, page 4-7.
Page 226: Video Display Field 2 Vertical Synchronization Start Register (Vdvsyns2)
4.12.19 Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2) The video display field 2 vertical synchronization start register (VDVSYNS2) controls the start of vertical synchronization in field 2. The VDVSYNS2 is shown in Figure 4–57 and described in Table 4–24. Generation of the vertical synchronization is shown in Figure 4–6, page 4-7.
Page 227: Video Display Field 2 Vertical Synchronization End Register (Vdvsyne2)
Video Display Registers 4.12.20 Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2) The video display field 2 vertical synchronization end register (VDVSYNE2) controls the end of vertical synchronization in field 2. The VDVSYNE2 is shown in Figure 4–58 and described in Table 4–25. Generation of the vertical synchronization is shown in Figure 4–6, page 4-7.
Page 228: Video Display Counter Reload Register (Vdreload)
4.12.21 Video Display Counter Reload Register (VDRELOAD) When external horizontal or vertical synchronization are used, the video display counter reload register (VDRELOAD) determines what values are loaded into the counters when an external sync is activated. The VDRELOAD is shown in Figure 4–59 and described in Table 4–26. Figure 4–59.
Page 229: Video Display Display Event Register (Vddispevt)
Video Display Registers 4.12.22 Video Display Display Event Register (VDDISPEVT) The video display display event register (VDDISPEVT) is programmed with the number of DMA events to be generated for display field 1 and field 2. The VDDISPEVET is shown in Figure 4–60 and described in Table 4–27. Figure 4–60.
Page 230: Video Display Clipping Register (Vdclip)
4.12.23 Video Display Clipping Register (VDCLIP) The video display clipping register (VDCLIP) is shown in Figure 4–61 and described in Table 4–28. The video display module in the BT.656 and Y/C modes performs program- mable clipping. The clipping is performed as the last step of the video pipeline. It is applied only on the image areas defined by VDIMGSZn and VDIMGOFFn inside the active video area (blanking values are not clipped).
Page 231: Video Display Default Display Value Register (Vddefval)
Video Display Registers 4.12.24 Video Display Default Display Value Register (VDDEFVAL) The video display default display value register (VDDEFVAL) defines the default value to be output during the portion of the active video window that is not part of the displayed image. The VDDEFVAL is shown in Figure 4–62 for the BT.656 and Y/C modes and in Figure 4–63 for the raw data mode, and described in Table 4–29.
Page 232: Video Display Default Display Value Register (Vddefval)-Raw Data Mode
Figure 4–63. Video Display Default Display Value Register (VDDEFVAL)—Raw Data Mode Reserved R/W-0 Legend: R/W = Read/Write; -n = value after reset Table 4–29. Video Display Default Display Value Register (VDDEFVAL) Field Descriptions † † field symval 31–24 CRDEFVAL OF(value) ‡...
Page 233: Video Display Vertical Interrupt Register (Vdvint)
Video Display Registers 4.12.25 Video Display Vertical Interrupt Register (VDVINT) The video display vertical interrupt register (VDVINT) controls the generation of vertical interrupts in field 1 and field 2. The VDVINT is shown in Figure 4–64 and described in Table 4–30. An interrupt can be generated upon completion of the specified line in a field (when FLCOUNT = VINTn).
Page 234: Video Display Field Bit Register (Vdfbit)
4.12.26 Video Display Field Bit Register (VDFBIT) The video display field bit register (VDFBIT) controls the F bit value in the EAV and SAV timing control codes. The VDFBIT is shown in Figure 4–65 and described in Table 4–31. The FBITCLR and FBITSET bits control the F bit value in the EAV and SAV timing control codes.
Page 235: Video Display Field 1 Vertical Blanking Bit Register (Vdvbit1)
Video Display Registers 4.12.27 Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1) The video display field 1 vertical blanking bit register (VDVBIT1) controls the V bit value in the EAV and SAV timing control codes for field 1. The VDVBIT1 is shown in Figure 4–66 and described in Table 4–32.
Page 236: Field Descriptions
Table 4–32. Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1) Field Descriptions † † field symval Value 31–28 Reserved – 27–16 VBITCLR1 OF(value) 0–FFFh 15–12 Reserved – 11–0 VBITSET1 OF(value) 0–FFFh † For CSL implementation, use the notation VP_VDVBIT1_field_symval SPRU629 Description BT.656 and Y/C Mode...
Page 237: Video Display Field 2 Vertical Blanking Bit Register (Vdvbit2)
Video Display Registers 4.12.28 Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2) The video display field 2 vertical blanking bit register (VDVBIT2) controls the V bit in the EAV and SAV timing control words for field 2. The VDVBIT2 is shown in Figure 4–67 and described in Table 4–33.
Page 238: Field Descriptions
Table 4–33. Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2) Field Descriptions † † field symval Value 31–28 Reserved – 27–16 VBITCLR2 OF(value) 0–FFFh 15–12 Reserved – 11–0 VBITSET2 OF(value) 0–FFFh † For CSL implementation, use the notation VP_VDVBIT2_field_symval SPRU629 Description BT.656 and Y/C Mode...
Page 239: Video Display Registers Recommended Values
Video Display Registers Recommended Values 4.13 Video Display Registers Recommended Values Sample recommended values (decimal) for video display registers for BT.656 output are given in Table 4–34. Table 4–34. Video Display Register Recommended Values Register Field VDFRMSZ FRMWIDTH FRMHEIGHT VDHBLNK HBLNKSTART HBLNKSTOP VDVBLKS1...
Page 240 Table 4–34. Video Display Register Recommended Values (Continued) Register Field VDVSYNS2 VSYNCXSTART2 VSYNCYSTART2 VDVSYNE2 VSYNCXSTOP2 VSYNCYSTOP2 VDFBIT FBITCLR FBITSET VDVBIT1 VBITSET1 VBITCLR1 VDVBIT2 VBITSET2 VBITCLR2 † Programming only required if external control signal is used. SPRU629 Video Display Registers Recommended Values 525/60 Value 625/50 Value †...
Page 241: Video Display Fifo Registers
Video Display FIFO Registers 4.14 Video Display FIFO Registers The display FIFO mapping registers are listed in Table 4–35. These registers provide DMA write access to the display FIFOs. These pseudo-registers should be mapped into DSP memory space rather than configuration register space in order to provide high-speed access.
Page 242: General Purpose I/O Operation
Chapter 5 General Purpose I/O Operation Signals not used for video display or video capture can be used as general- purpose input/output (GPIO) signals. Topic Page GPIO Registers ..........
Page 243: Gpio Registers
GPIO Registers 5.1 GPIO Registers The GPIO register set includes required registers such as peripheral identifi- cation and emulation control. The GPIO registers are listed in Table 5–1. See the device-specific datasheet for the memory address of these registers. Table 5–1. Video Port Registers Acronym Register Name VPPID...
Page 244: Video Port Peripheral Identification Register (Vppid)
5.1.1 Video Port Peripheral Identification Register (VPPID) The video port peripheral identification register (VPPID) is a read-only register used to store information about the peripheral. The VPPID is shown in Figure 5–1 and described in Table 5–2. Figure 5–1. Video Port Peripheral Identification Register (VPPID) Reserved CLASS R-0000 1001...
Page 245: Video Port Peripheral Control Register (Pcr)
GPIO Registers 5.1.2 Video Port Peripheral Control Register (PCR) The video port peripheral control register (PCR) determines operation during emulation. The video port peripheral control register is shown in Figure 5–2 and described in Table 5–3. Normal operation is to not halt the port during emulation suspend. This allows a displayed image to remain visible during suspend.
Page 246: Video Port Peripheral Control Register (Pcr) Field Descriptions
Table 5–3. Video Port Peripheral Control Register (PCR) Field Descriptions † † field symval Value 31–3 Reserved PEREN DISABLE ENABLE SOFT STOP COMP FREE SOFT † For CSL implementation, use the notation VP_PCR_field_symval SPRU629 Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Page 247: Video Port Pin Function Register (Pfunc)
GPIO Registers 5.1.3 Video Port Pin Function Register (PFUNC) The video port pin function register (PFUNC) selects the video port pins as GPIO. The PFUNC is shown in Figure 5–3 and described in Table 5–4. Each bit controls either one pin or a set of pins. When a bit is set to 1, it enables the pin(s) that map to it as GPIO.
Page 248 Table 5–4. Video Port Pin Function Register (PFUNC) Field Descriptions (Continued) † † field symval PFUNC20 NORMAL VCTL1 19–11 Reserved – PFUNC10 NORMAL VDATA10TO19 9–1 Reserved – PFUNC0 NORMAL VDATA0TO9 † For CSL implementation, use the notation VP_PFUNC_field_symval SPRU629 Value Description PFUNC20 bit determines if VCTL1 pin functions as GPIO.
Page 249: Video Port Pin Direction Register (Pdir)
GPIO Registers 5.1.4 Video Port Pin Direction Register (PDIR) The video port pin direction register (PDIR) is shown in Figure 5–4 and described in Table 5–5. The PDIR controls the direction of IO pins in the video port for those pins set by PFUNC. If a bit is set to 1, the relevant pin or pin group acts as an output.
Page 250 Table 5–5. Video Port Pin Direction Register (PDIR) Field Descriptions (Continued) † † field symval PDIR21 VCTL2IN VCTL2OUT PDIR20 VCTL1IN VCTL1OUT 19–17 Reserved – PDIR16 VDATA16TO19IN VDATA16TO19OUT 15–13 Reserved – PDIR12 VDATA12TO15IN VDATA12TO15OUT Reserved – PDIR10 VDATA10TO11IN VDATA10TO11OUT Reserved – †...
Page 251 GPIO Registers Table 5–5. Video Port Pin Direction Register (PDIR) Field Descriptions (Continued) † † field symval PDIR8 VDATA8TO9IN VDATA8TO9OUT 7–5 Reserved – PDIR4 VDATA4TO7IN VDATA4TO7OUT 3–1 Reserved – PDIR0 VDATA0TO3IN VDATA0TO3OUT † For CSL implementation, use the notation VP_PDIR_field_symval 5-10 General Purpose I/O Operation Value...
Page 252: Video Port Pin Data Input Register (Pdin)
5.1.5 Video Port Pin Data Input Register (PDIN) The read-only video port pin data input register (PDIN) is shown in Figure 5–5 and described in Table 5–6. PDIN reflects the state of the video port pins. When read, PDIN returns the value from the pin’s input buffer (with appropriate synchronization) regardless of the state of the corresponding PFUNC or PDIR bit.
Page 253: Video Port Pin Data Input Register (Pdin) Field Descriptions
GPIO Registers Table 5–6. Video Port Pin Data Input Register (PDIN) Field Descriptions † † field symval Value 31–23 Reserved – PDIN22 VCTL3LO VCTL3HI PDIN21 VCTL2LO VCTL2HI PDIN20 VCTL1LO VCTL1HI 19–0 PDIN[19–0] VDATAnLO VDATAnHI † For CSL implementation, use the notation VP_PDIN_PDINn_symval 5-12 General Purpose I/O Operation Description...
Page 254: Video Port Pin Data Output Register (Pdout)
5.1.6 Video Port Pin Data Output Register (PDOUT) The video port pin data output register (PDOUT) is shown in Figure 5–6 and described in Table 5–7. The bits of PDOUT determine the value driven on the corresponding GPIO pin, if the pin is configured as an output. Writes do not affect pins not configured as GPIO outputs.
Page 255: Video Port Pin Data Out Register (Pdout) Field Descriptions
GPIO Registers Table 5–7. Video Port Pin Data Out Register (PDOUT) Field Descriptions † † field symval 31–23 Reserved – PDOUT22 VCTL3LO VCTL3HI PDOUT21 VCTL2LO VCTL2HI PDOUT20 VCTL1LO VCTL1HI 19–0 PDOUT[19–0] VDATAnLO VDATAnHI † For CSL implementation, use the notation VP_PDOUT_PDOUTn_symval 5-14 General Purpose I/O Operation Value...
Page 256: Video Port Pin Data Set Register (Pdset)
5.1.7 Video Port Pin Data Set Register (PDSET) The video port pin data set register (PDSET) is shown in Figure 5–7 and described in Table 5–8. PDSET is an alias of the video port pin data output reg- ister (PDOUT) for writes only and provides an alternate means of driving GPIO outputs high.
Page 257: Video Port Pin Data Set Register (Pdset) Field Descriptions
GPIO Registers Table 5–8. Video Port Pin Data Set Register (PDSET) Field Descriptions † † field symval 31–23 Reserved – PDSET22 NONE VCTL3HI PDSET21 NONE VCTL2HI PDSET20 NONE VCTL1HI 19–0 PDSET[19–0] NONE VDATAnHI † For CSL implementation, use the notation VP_PDSET_PDSETn_symval 5-16 General Purpose I/O Operation Value...
Page 258: Video Port Pin Data Clear Register (Pdclr)
5.1.8 Video Port Pin Data Clear Register (PDCLR) The video port pin data clear register (PDCLR) is shown in Figure 5–8 and described in Table 5–9. PDCLR is an alias of the video port pin data output reg- ister (PDOUT) for writes only and provides an alternate means of driving GPIO outputs low.
Page 259: Video Port Pin Data Clear Register (Pdclr) Field Descriptions
GPIO Registers Table 5–9. Video Port Pin Data Clear Register (PDCLR) Field Descriptions † † field symval 31–23 Reserved – PDCLR22 NONE VCTL3CLR PDCLR21 NONE VCTL2CLR PDCLR20 NONE VCTL1CLR 19–0 PDCLR[19–0] NONE VDATAnCLR † For CSL implementation, use the notation VP_PDCLR_PDCLRn_symval 5-18 General Purpose I/O Operation Value...
Page 260: Video Port Pin Interrupt Enable Register (Pien)
5.1.9 Video Port Pin Interrupt Enable Register (PIEN) The video port pin interrupt enable register (PIEN) is shown in Figure 5–9 and described in Table 5–10. The GPIOs can be used to generate DSP interrupts or DMA events. The PIEN selects which pins may be used to generate an interrupt.
Page 261: Video Port Pin Interrupt Enable Register (Pien) Field Descriptions
GPIO Registers Table 5–10. Video Port Pin Interrupt Enable Register (PIEN) Field Descriptions † † field symval Value 31–23 Reserved – PIEN22 VCTL3LO VCTL3HI PIEN21 VCTL2LO VCTL2HI PIEN20 VCTL1LO VCTL1HI 19–0 PIEN[19–0] VDATAnLO VDATAnHI † For CSL implementation, use the notation VP_PIEN_PIENn_symval 5-20 General Purpose I/O Operation Description...
Page 262: Video Port Pin Interrupt Polarity Register (Pipol)
5.1.10 Video Port Pin Interrupt Polarity Register (PIPOL) The video port pin interrupt polarity register (PIPOL) is shown in Figure 5–10 and described in Table 5–11. The PIPOL determines the GPIO pin signal polarity that generates an interrupt. Figure 5–10. Video Port Pin Interrupt Polarity Register (PIPOL) Reserved PIPOL22 PIPOL21...
Page 263: Video Port Pin Interrupt Polarity Register (Pipol) Field Descriptions
GPIO Registers Table 5–11. Video Port Pin Interrupt Polarity Register (PIPOL) Field Descriptions † † field symval 31–23 Reserved – PIPOL22 VCTL3ACTHI VCTL3ACTLO PIPOL21 VCTL2ACTHI VCTL2ACTLO PIPOL20 VCTL1ACTHI VCTL1ACTLO 19–0 PIPOL[19–0] VDATAnACTHI VDATAnACTLO † For CSL implementation, use the notation VP_PIPOL_PIPOLn_symval 5-22 General Purpose I/O Operation Value...
Page 264: Video Port Pin Interrupt Status Register (Pistat)
5.1.11 Video Port Pin Interrupt Status Register (PISTAT) The video port pin interrupt status register (PISTAT) is shown in Figure 5–11 and described in Table 5–12. PISTAT is a read-only register that indicates the GPIO pin that has a pending interrupt. A bit in PISTAT is set when the corresponding GPIO pin is configured as an interrupt (the corresponding bit in PIEN is set, the pin is enabled for GPIO in PFUNC, and the pin is configured as an input in PDIR) and the appropriate...
Page 265: Video Port Pin Interrupt Status Register (Pistat) Field Descriptions
GPIO Registers Table 5–12. Video Port Pin Interrupt Status Register (PISTAT) Field Descriptions † † field symval 31–23 Reserved – PISTAT22 NONE VCTL3INT PISTAT21 NONE VCTL2INT PISTAT20 NONE VCTL1INT 19–0 PISTAT[19–0] NONE VDATAnINT † For CSL implementation, use the notation VP_PISTAT_PISTATn_symval 5-24 General Purpose I/O Operation Value...
Page 266: Video Port Pin Interrupt Clear Register (Piclr)
5.1.12 Video Port Pin Interrupt Clear Register (PICLR) The video port pin interrupt clear register (PICLR) is shown in Figure 5–12 and described in Table 5–13. PICLR is an alias of the video port pin interrupt status register (PISTAT) for writes only. Writing a 1 to a bit of PICLR clears the corre- sponding bit in PISTAT.
Page 267: Video Port Pin Interrupt Clear Register (Piclr) Field Descriptions
GPIO Registers Table 5–13. Video Port Pin Interrupt Clear Register (PICLR) Field Descriptions † † field symval 31–23 Reserved – PICLR22 NONE VCTL3CLR PICLR21 NONE VCTL2CLR PICLR20 NONE VCTL1CLR 19–0 PICLR[19–0] NONE VDATAnCLR † For CSL implementation, use the notation VP_PICLR_PICLRn_symval 5-26 General Purpose I/O Operation Value...
Page 268: Vcxo Interpolated Control Port
VCXO Interpolated Control Port This chapter provides an overview of the VCXO interpolated control (VIC) port. Topic Overview Interface Operational Details Enabling VIC Port VIC Port Registers SPRU629 ............
Page 269: Overview
Overview 6.1 Overview The VCXO interpolated control (VIC) port provides single-bit interpolated VCXO control with resolution from 9 bits to up to 16 bits. The frequency of inter- polation is dependent on the resolution needed. When the video port is used in transport stream interface (TSI) mode, the VIC port is used to control the system clock, VCXO, for MPEG transport stream (Figure 6–1).
Page 270: Interface
6.2 Interface The pin list for VIC port is shown in Table 6–1 (pins are 3.3V I/Os). Table 6–1. VIC Port Interface Signals VIC Port Signal VCTL STCLK 6.3 Operational Details Synchronization is an important aspect of decoding and presenting data in real-time digital data delivery systems.
Page 271: Example Values For Interpolation Rate
Operational Details Any time a packet with a PCR is received, the timestamp for that packet is compared with the PCR value in software. A PLL is implemented in software to synchronize the STCLK with the system time clock. The DSP updates the VIC input register (VICIN) using the output from this algorithm, which in turn drives the VCTL output that controls the system time clock VCXO.
Page 272: Enabling Vic Port
6.4 Enabling VIC Port Perform the following steps to enable the VIC port. 1) Clear the GO bit in the VIC control register (VICCTL) to 0. 2) Set the PRECISION bits in VICCTL to the desired precision. 3) Set the VIC clock divider register (VICDIV) bits to appropriate value based on the precision and interpolation frequency.
Page 273: Vic Control Register (Vicctl)
VIC Port Registers 6.5.1 VIC Control Register (VICCTL) The VIC control register (VICCTL) is shown in Figure 6–3 and described in Table 6–4. Figure 6–3. VIC Control Register (VICCTL) Reserved Legend: R = Read only; R/W = Read/Write; -n = value after reset Table 6–4.
Page 274: Vic Port Registers
Table 6–4. VIC Control Register (VICCTL) Field Descriptions (Continued) † † field symval Value † For CSL implementation, use the notation VIC_VICCTL_field_symval SPRU629 Description The GO bit can be written to at any time. The VICDIV and VICCTL registers can be written to without affecting the operation of the VIC port.
Page 275: Vic Input Register (Vicin)
VIC Port Registers 6.5.2 VIC Input Register (VICIN) The DSP writes the input bits for VCXO interpolated control in the VIC input register (VICIN). The DSP decides how often to update VICIN. The DSP can write to VICIN only when the GO bit in the VIC control register (VICCTL) is set to 1.
Page 276: Vic Clock Divider Register (Vicdiv)
6.5.3 VIC Clock Divider Register (VICDIV) The VIC clock divider register (VICDIV) defines the clock divider for the VIC interpolation frequency. The VIC interpolation frequency is obtained by divid- ing the module clock. The divider value written to VICDIV is: where DCLK is the CPU clock divided by 2, and R is the desired interpolation frequency.
Page 277: Video Port Configuration Examples
Video Port Configuration Examples This appendix describes how to configure the video port in different modes with the help of examples. All examples in this appendix use the video port Chip Support Library (CSL). Topic Example 1: Noncontinuous Frame Capture for 525/60 Format Example 2: Noncontinuous Frame Display for 525/60 Format Appendix A Appendix A...
Page 278: Example 1: Noncontinuous Frame Capture For 525/60 Format
Example 1: Noncontinuous Frame Capture for 525/60 Format A.1 Example 1: Noncontinuous Frame Capture for 525/60 Format This is an example that explains how to configure the video port for 8-bit BT.656 noncontinuous frame capture on channel A for 525/60 format. See ITU–R BT.656-4 and video port specification (Figures 4–11, 4–33, 4–34, and Table 4–37) for more details on 525/60 format.
Page 279 /* –––––––––––––––––––––––––––––––––––––––––––– */ /* EDMA parameters for capture Y event that are */ /* specific to this example. /* –––––––––––––––––––––––––––––––––––––––––––– */ #define VCA_Y_EDMA_ELECNT (VCA_THRLD_FIELD1 * 2) in double–words and element size is 32–bit */ #define VCA_Y_EDMA_FRMCNT ((VCA_CAPEVT1 + VCA_CAPEVT2) * CAPCHA_FRAME_COUNT) /******************************************************************/ /* Description : 8–bit BT.656 non–continuous frame capture...
Page 280 Example 1: Noncontinuous Frame Capture for 525/60 Format /* Error flags volatile Uint32 capChaAOverrun = 0; volatile Uint32 capChaASyncError = 0; volatile Uint32 capChaAShortFieldDetect = 0; volatile Uint32 capChaALongFieldDetect = 0; /* ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– */ /* Function : bt656_8bit_ncfc /* Input(s) : portNumber, video port number i.e.
Page 281 /* Set last pixel to be captured in Field2 (VCA_STOP2 reg) VP_RSETH(vpCaptureHandle, VCASTOP2, VP_VCASTOP2_RMK(VCA_YSTOP2, VCA_XSTOP2)); /* Set first pixel to be captured in Field1 (VCA_STRT1 reg) VP_RSETH(vpCaptureHandle, VCASTRT1, VP_VCASTRT1_RMK(VCA_YSTART1, VP_VCASTRT1_SSE_ENABLE, VCA_XSTART1)); /* Set first pixel to be captured in Field2 (VCA_STRT2 reg) VP_RSETH(vpCaptureHandle, VCASTRT2, VP_VCASTRT2_RMK(VCA_YSTART2, VCA_XSTART2));...
Page 282 Example 1: Noncontinuous Frame Capture for 525/60 Format /* –––––––––––––– */ /* enable capture */ /* –––––––––––––– */ /* set VCEN bit to enable capture VP_FSETH(vpCaptureHandle, VCACTL, VCEN, VP_VCACTL_VCEN_ENABLE); /* clear BLKCAP in VCA_CTL to enable capture DMA events VP_FSETH(vpCaptureHandle, VCACTL, BLKCAP, VP_VCACTL_BLKCAP_CLEAR);...
Page 283 if(vpis & _VP_VPIS_SFDA_MASK) /* short field detect capChaAShortFieldDetect++; VP_FSETH(vpCaptureHandle, VPIS, SFDA, VP_VPIS_SFDA_CLEAR); if(vpis & _VP_VPIS_LFDA_MASK) /* long field detect capChaALongFieldDetect++; VP_FSETH(vpCaptureHandle, VPIS, LFDA, VP_VPIS_LFDA_CLEAR); /*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– */ /* Function : setupVPCapChaAEDMA /* Input(s) : portNumber, video port number i.e. 0, 1 or 2. /* Description : Sets up EDMA channels for Y, U, V events for channel A capture.
Page 284 Example 1: Noncontinuous Frame Capture for 525/60 Format /* Configure Cb EDMA channel to move data from CbSRCA /* (FIFO) to Cb–data buffer, capChaACbSpace configVPCapEDMAChannel(&hEdmaVPCapChaACb, UEvent, &edmaCapChaACbTccNum, vpCaptureHandle–>cbsrcaAddr, (Uint32)capChaACbSpace, VCA_Y_EDMA_FRMCNT, VCA_Y_EDMA_ELECNT/2); /* (1/2) of Y–samples /* Configure Cr EDMA channel to move data from CrSRCA /* (FIFO) to Cr–data buffer, capChaACrSpace configVPCapEDMAChannel(&hEdmaVPCapChaACr, VEvent, &edmaCapChaACrTccNum,...
Page 285 void configVPCapEDMAChannel(EDMA_Handle *edmaHandle, Int32 eventId, Int32 *tccNum, Uint32 srcAddr, Uint32 dstAddr, Uint32 frameCount, Uint32 elementCount) Int32 tcc = 0; /* Open Y EVT EDMA channel *edmaHandle = EDMA_open(eventId, EDMA_OPEN_RESET); if(*edmaHandle == EDMA_HINV) test_exit(FAIL); /* allocate TCC for Y event if((tcc = EDMA_intAlloc(–1)) == –1) test_exit(FAIL);...
Page 286: Example 2: Noncontinuous Frame Display For 525/60 Format
Example 2: Noncontinuous Frame Display for 525/60 Format A.2 Example 2: Noncontinuous Frame Display for 525/60 Format This is an example that explains how to configure the video port for 8-bit BT.656 noncontinuous frame display for 525/60 format. See ITU–R BT.656–4 and video port specification (Figures 4–11, 4–33, 4–34, and Table 4–37) for more details on 525/60 format.
Page 287 /* ––––––––––––––––––––––––––––––––––––––––––––––––– */ /* Define vertical blanking bit(VD_VBITn) reg values */ /* ––––––––––––––––––––––––––––––––––––––––––––––––– */ #define VD_VBIT_SET1 #define VD_VBIT_CLR1 #define VD_VBLNK1_SIZE (VD_VBIT_CLR1 – VD_VBIT_SET1) /* 19 lines #define VD_VBIT_SET2 264 /* first line with an EAV with V=1 #define VD_VBIT_CLR2 283 /* first line with an EAV with V=0 #define VD_VBLNK2_SIZE (VD_VBIT_CLR2 –...
Page 288 Example 2: Noncontinuous Frame Display for 525/60 Format /* –––––––––––––––––––––––––––––––––––––––––– */ /* Define vertical synchronization for field2 */ /* –––––––––––––––––––––––––––––––––––––––––– */ #define VD_VSYNC_XSTART2 #define VD_VSYNC_YSTART2 #define VD_VSYNC_XSTOP2 #define VD_VSYNC_YSTOP2 /* –––––––––––––––––––––––––––––––––––––––– */ /* Define image offsets for both the fields */ /* which are zero in this example /* ––––––––––––––––––––––––––––––––––––––––...
Page 289 /******************************************************************/ /* Description : 8–bit BT.656 non–continuous frame display /* Some important field descriptions: /* DMODE = 000, 8–bit BT.656 mode /* CON /* FRAME = 1, display frame /* DF2 /* DF1 = 0, (8–bit non–continuous frame display) /* SCALE = 0, no scaling /* RESMPL = 0, no resampling /* DPK...
Page 290 Example 2: Noncontinuous Frame Display for 525/60 Format /*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– */ /* Function : bt656_8bit_ncfd /* Input(s) : portNumber, video port number i.e. 0, 1 or 2. /* Description : Configures given video port for 8–bit BT.656 non– */ continuous frame display. /*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––...
Page 291 /* set vertical blanking start for field2 VP_RSETH(vpDisplayHandle , VDVBLKS2, VP_VDVBLKS2_RMK(VD_VBLNK_YSTART2, VD_VBLNK_XSTART2)); /* set vertical blanking end for field2 VP_RSETH(vpDisplayHandle , VDVBLKE2, VP_VDVBLKE2_RMK(VD_VBLNK_YSTOP2, VD_VBLNK_XSTOP2)); /* set vertical blanking bit register for field 1(VD_VBIT1) VP_RSETH(vpDisplayHandle , VDVBIT1, VP_VDVBIT1_RMK(VD_VBIT_CLR1, VD_VBIT_SET1)); /* set vertical blanking bit register for field 2(VD_VBIT2) VP_RSETH(vpDisplayHandle , VDVBIT2, VP_VDVBIT2_RMK(VD_VBIT_CLR2, VD_VBIT_SET2));...
Page 292 Example 2: Noncontinuous Frame Display for 525/60 Format /* set vertical sync end for field2 (VCTL2S) VP_RSETH(vpDisplayHandle , VDVSYNE2, VP_VDVSYNE2_RMK(VD_VSYNC_YSTOP2, VD_VSYNC_XSTOP2)); /* Let clipping values to be their defaults (VD_CLIP) /* No need to set DEF_VAL and VD_RELOAD in this example /* set event register VP_RSETH(vpDisplayHandle , VDDISPEVT, VP_VDDISPEVT_RMK(VD_DISPEVT2, VD_DISPEVT1));...
Page 293 /* –––––––––––––– */ /* enable display */ /* –––––––––––––– */ /* set VDEN to enable display for loop–back VP_FSETH(vpBDisplayHandle, VDCTL, VDEN, VP_VDCTL_VDEN_ENABLE); /* clear BLKDIS in VD_CTL to enable display DMA events VP_FSETH(vpBDisplayHandle, VDCTL, BLKDIS, VP_VDCTL_BLKDIS_CLEAR); /*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– */ /* Function : VPDispIsr /* Description : This display ISR clears FRMD to continue display in this non–continuous mode and also clears other */...
Page 294 Example 2: Noncontinuous Frame Display for 525/60 Format /*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– */ /* Function : setupVPDispEDMA /* Input(s) : portNumber, video port number i.e. 0,1 or 2. /* Description : Sets up DMA channels for Y, U, V events for VP display. /*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––...
Page 295 /* enable three EDMA channels EDMA_enableChannel(hEdmaVPDispY); EDMA_enableChannel(hEdmaVPDispCb); EDMA_enableChannel(hEdmaVPDispCr); /*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– /* Function : configVPDispEDMAChannel /* Input(s) : edmaHandle eventId tccNum srcAddr dstAddr frameCount elementCount /* Output(s): edmaHandle tccNum /* Description : Configures the given VP display EDMA channel. The destination address update is fixed because the displayed data is write to the FIFO.
Page 296 Example 2: Noncontinuous Frame Display for 525/60 Format /* Configure EDMA parameters EDMA_configArgs( *edmaHandle, EDMA_OPT_RMK( EDMA_OPT_PRI_MEDIUM, EDMA_OPT_ESIZE_32BIT, EDMA_OPT_2DS_YES, EDMA_OPT_SUM_INC, EDMA_OPT_2DD_NO, EDMA_OPT_DUM_NONE, EDMA_OPT_TCINT_YES, EDMA_OPT_TCC_OF(tcc & 0xF), EDMA_OPT_TCCM_OF(((tcc & 0x30) >> 4)), EDMA_OPT_ATCINT_NO, EDMA_OPT_ATCC_OF(0), EDMA_OPT_PDTS_DISABLE, /* disable PDT(peripheral device EDMA_OPT_PDTD_DISABLE, /* disable PDT mode for dest EDMA_OPT_LINK_NO, EDMA_OPT_FS_NO EDMA_SRC_RMK(srcAddr),...
Page 297 ancillary data capture 3-31 ancillary data display 4-25 architecture 1-3 ATC bit in TSISTCMPL 3-78 in TSISTCMPM 3-79 ATCM bit in TSISTMSKL 3-80 in TSISTMSKM 3-81 BLKCAP bit in VCACTL 3-53 in VCBCTL 3-68 BLKDIS bit 4-55 block diagrams 16/20-bit raw video capture FIFO configuration 1-9 16/20-bit raw video display FIFO configuration 1-11...
Page 298 Index CbDEFVAL bits 4-86 CBDST 4-96 CBSRCx 3-83 CCMPA bit in VPIE 2-21 in VPIS 2-24 CCMPB bit in VPIE 2-21 in VPIS 2-24 CF1 bit in VCACTL 3-53 in VCBCTL 3-68 CF2 bit in VCACTL 3-53 in VCBCTL 3-68 CLASS bits 5-3 CLIPCHIGH bits 4-85 CLIPCLOW bits 4-85...
Page 299 F1C bit 3-50 F1D bit 4-53 F2C bit 3-50 F2D bit 4-53 FBITCLR bits 4-89 FBITSET bits 4-89 FIFO overrun BT.656 mode 3-45 raw data mode 3-47 TSI capture mode 3-48 video display 4-51 Y/C mode 3-45 FIFO packing BT.656 mode 3-9 raw data mode 3-33 TSI capture mode 3-41 Y/C mode 3-14...
Page 300 Index LFDE bit in VCACTL 3-53 in VCBCTL 3-68 mode selection TSI capture 3-2 video capture 3-2 video display 4-2 NH bit in VDIMGOFF1 4-69 in VDIMGOFF2 4-71 noncontinuous frame capture for 525/60 format example A-2 noncontinuous frame display for 525/60 format example A-10 notational conventions iii NV bit...
Page 301 registers (continued) VIC port 6-5 VIC clock divider register (VICDIV) 6-9 VIC control register (VICCTL) 6-6 VIC input register (VICIN) 6-8 video capture 3-49 Cb FIFO source register (CBSRCx) 3-83 channel A control register (VCACTL) 3-53 channel A event count register (VCAEVTCT) 3-67 channel A field 1 start register (VCASTRT1) 3-58...
Page 302 (PICLR) 5-25 pin interrupt enable register (PIEN) 5-19 pin interrupt polarity register (PIPOL) 5-21 pin interrupt status register (PISTAT) 5-23 status register (VPSTAT) 2-20 related documentation from Texas Instruments iii reset operation 2-2 RESMPL 4-55 RESMPL bit in VCACTL 3-53...
Page 303 TSI clock initialization LSB register (TSICLKINITL) 3-74 TSI clock initialization MSB register (TSICLKINITM) 3-75 TSI system time clock compare LSB register (TSISTCMPL) 3-78 TSI system time clock compare mask LSB register (TSISTMSKL) 3-80 TSI system time clock compare mask MSB register (TSISTMSKM) 3-81 TSI system time clock compare MSB register (TSISTCMPM) 3-79...
Page 304 Index VDCLIP 4-85 VDCTL 4-55 VDDEFVAL 4-86 VDDISPEVT 4-84 VDEN 4-55 VDFBIT 4-89 VDFLD bit 4-53 VDFLDT1 4-74 VDFLDT2 4-75 VDFRMSZ 4-60 VDHBLNK 4-61 VDHSYNC 4-78 VDIMGOFF1 4-68 VDIMGOFF2 4-71 VDIMGSZ1 4-70 VDIMGSZ2 4-73 VDRELOAD 4-83 VDSTAT 4-53 VDTHRLD 4-76 VDTHRLD1 bits 4-76 VDTHRLD2 bits 4-76 VDVBIT1 4-90...
Page 305 video capture channel B vertical interrupt register (VCBVINT) 3-63 video capture FIFO configurations 1-6 video capture mode BT.656 3-3 raw data 3-32 TSI 3-37 Y/C 3-12 video display counters 4-5 external sync operation 4-8 FIFO configurations 1-9 FIFO overrun 4-51 FIFO registers 4-96 image timing 4-2 mode selection 4-2...
Page 306 Index video port FIFO 1-5 video port interrupt enable register (VPIE) 2-21 video port interrupt status register (VPIS) 2-24 video port peripheral control register (PCR) 5-4 video port peripheral identification register (VPPID) 5-3 video port pin data clear register (PDCLR) 5-17 video port pin data input register (PDIN) 5-11 video port pin data output register (PDOUT) 5-13 video port pin data set register (PDSET) 5-15...

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Tms320c6000

Texas Instruments TMS320C64x DSP Reference Manual

Overview

Video Port

Chapter 2

Reset Operation

Interrupt Operation

DMA Operation

Clocks

Video Port Functionality Subsets

Video Port Throughput and Latency

Video Port Control Registers

Video Capture Port

Video Display Port

Chapter 4

Video Display Mode Selection

BT.656 Video Display Mode

Y/C Video Display Mode

Video Output Filtering

Ancillary Data Display

Raw Data Display Mode

Video Display Field and Frame Operation

Display Line Boundary Conditions

Display Timing Examples

Displaying Video in BT.656 or Y/C Mode

Displaying Video in Raw Data Mode

Video Display Registers

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Summary of Contents for Texas Instruments TMS320C64x DSP