Single-Cycle Instructions; Single-Cycle Instruction Phases; Single-Cycle Execution Block Diagram; Single-Cycle Execution - Texas Instruments TMS320C6000 Series Reference Manual

Functional Unit Hazards
6.3.5

Single-Cycle Instructions

Table 6–20. Single-Cycle Execution
Figure 6–8. Single-Cycle Instruction Phases
Figure 6–9. Single-Cycle Execution Block Diagram
6-38
Single-cycle instructions complete execution during the E1 phase of the pipe-
line (see Table 6–20). Figure 6–8 shows the fetch, decode, and execute
phases of the pipeline that single-cycle instructions use. Figure 6–9 is the
single-cycle execution diagram. The operands are read, the operation is per-
formed, and the results are written to a register, all during E1. Single-cycle
instructions have no delay slots.
PG
Operands
(data)
Pipeline
Stage E1
Read src1
src2
Written dst
Unit in use .L, .S., .M, or
.D
PS PW PR DP
Functional
unit
.L, .S, .M,
or .D
Write results
Register file
DC E1
E1