Multiply Execution Block Diagram; Store Instruction Phases - Texas Instruments TMS320C6000 Series Reference Manual

Figure 5–11.Multiply Execution Block Diagram
5.2.3 Store Instructions
Figure 5–12. Store Instruction Phases
Figure 5–11 shows the operations occurring in the pipeline for a multiply. In the
E1 phase, the operands are read and the multiply begins. In the E2 phase, the
multiply finishes, and the result is written to the destination register. Multiply
instructions have one delay slot.
Operands
(data)
Store instructions require phases E1 through E3 to complete their operations.
Figure 5–12 shows the pipeline phases the store instructions use.
PG PS
Figure 5–13 shows the operations occurring in the pipeline phases for a store.
In the E1 phase, the address of the data to be stored is computed. In the E2
phase, the data and destination addresses are sent to data memory. In the E3
phase, a memory write is performed. The address modification is performed
in the E1 stage of the pipeline. Even though stores finish their execution in the
E3 phase of the pipeline, they have no delay slots.
Pipeline Execution of Instruction Types
Functional
unit
.M
Write results
E1
Register file
PW PR DP DC
TMS320C62x Pipeline
E2
E1 E2 E3
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